Abstract: A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Abstract: A refresh control device for reducing power consumption during a target row refresh operation is disclosed. The refresh control device includes a refresh address generator configured to generate a refresh address by selecting any one of a target row refresh address and a normal refresh address according to a target row refresh flag signal, an address control signal generator configured to generate a multiple address control signal in response to the target row refresh flag signal and a multiple refresh signal, and a final refresh address generator configured to generate a plurality of final refresh addresses from the refresh address in response to the multiple address control signal.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.

Abstract: A memory device includes a plurality of banks suitable for including a plurality of word lines, a plurality of latch units each suitable for generating a first address by inverting a predetermined bit of an address of an activated word line of a corresponding bank and latching the first address as a target address in sections other than a target refresh section, and latching an operation address as the target address once in an all-bank refresh section of the target refresh section, wherein all of the plurality of banks are refreshed in the all-bank refresh section. All the plurality of banks are refreshed in the all-bank refresh section, and an address operation unit suitable for generating the operation address by adding or subtracting an operation value to or from the target address. A word line among the plurality of word lines that is selected using the target address may be refreshed in the target refresh section.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.

Abstract: A memory device includes a plurality of banks suitable for including a plurality of word lines, a plurality of latch units each suitable for generating a first address by inverting a predetermined bit of an address of an activated word line of a corresponding bank and latching the first address as a target address in sections other than a target refresh section, and latching an operation address as the target address once in an all-bank refresh section of the target refresh section, wherein all of the plurality of banks are refreshed in the all-bank refresh section. All the plurality of banks are refreshed in the all-bank refresh section, and an address operation unit suitable for generating the operation address by adding or subtracting an operation value to or from the target address. A word line among the plurality of word lines that is selected using the target address may be refreshed in the target refresh section.

Abstract: A semiconductor device may include a refresh controller and a bank active signal generator. The refresh controller may be suitable for generating a level signal, setting a level of the level signal in response to a refresh pulse signal while operating in a test mode, and suitable for receiving a refresh flag signal and generating a first period signal and a second period signal in response to the level signal. The bank active signal generator may be suitable for generating bank active signals for a first bank group in response to the first period signal, and generating bank active signals for a second bank group in response to the second period signal.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.

Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.