Abstract: Methods for analyzing the connected quality of a hydrocarbon reservoir are disclosed. A model of a portion of the reservoir is divided into cells, each cell having a volume and some attributes, and wherein a speed function is assigned to a portion of the cells. A reference cell is chosen. A connectivity between cells in the reservoir is determined by solving an Eikonal equation that describes the travel time propagation, said propagating front progressing outward from a reference cell until an ending condition is met, said Eikonal equation being solved by a fast marching method with propagation velocity as a function of spatial position being provided by the speed function. Regions of the reservoir are characterized by their connective quality to the reference cell using the connectivity.

Abstract: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.

Abstract: Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.

Abstract: A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: A method to extract fault surfaces from seismic data (1,3) is disclosed. The method comprises: (a) generating at least two fault sticks (5) from the same fault from at least two slices of the seismic data wherein each slice comprises at least one fault stick from the same fault, (b) constructing an initial three-dimensional fault surface (7) containing the fault sticks, and (c) reconstructing the initial fault surface (9) using a deformable surface model to fit discontinuity or coherency information in the seismic data in an iterative process. Techniques are disclosed for constructing the initial fault surface from interpreter-provided fault nodes, and for performing the deformable surface iteration by defining an energy function for the fault surface and then minimizing the surface energy.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Abstract: In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device.

Abstract: In a method of manufacturing a semiconductor device for use in such applications as a flash memory device, a field insulating pattern defines an opening that exposes an active region of a semiconductor substrate. The field insulating pattern includes a first portion protruding from the substrate and a second portion buried in the substrate. An oxide layer is formed on the active region by an oxidation process using a reactive plasma including an oxygen radical and a conductive layer is then formed on the oxide layer to sufficiently fill up the opening. The oxide layer is formed by an oxidation reaction of a surface portion of the active region with the oxygen radical having a relatively low activation energy, resulting in an improved thickness uniformity of the oxide layer. As a result, various performance characteristics of the semiconductor device when used in flash memory and similar applications are improved.

Abstract: In a method of forming a thin-film structure employed in a non-volatile semiconductor device, an oxide film is formed on a substrate. An upper nitride film is formed on the oxide film by nitrifying an upper portion of the oxide film through a plasma nitration process. A lower nitride film is formed between the substrate and the oxide film by nitrifying a lower portion of the oxide film through a thermal nitration process. A damage to the thin-film structure generated in the plasma nitration process may be at least partially cured in the thermal nitration process, and/or may be cured in a post-thermal treatment process.

Abstract: Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Abstract: Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region.

Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.