Patents by Inventor Chul Sung

Chul Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190038717
    Abstract: A recombinant lentiviral vector includes a gene encoding a hepatocyte growth factor (HGF) protein. And a cell that is transfected with the lentivirus produced by using the vector is provided. The recombinant lentivirus includes a gene encoding a HGF protein, and a host cell transfected with the lentivirus maintains a high cell proliferation rate. Thus, a mesenchymal stem cell expressing HGF by being transfected with the lentivirus may be usefully employed as a cell therapeutic agent.
    Type: Application
    Filed: February 6, 2017
    Publication date: February 7, 2019
    Applicant: SLBIGEN INC.
    Inventors: Young Chul SUNG, Soon Min LEE, Hey-yon KIM
  • Publication number: 20190038676
    Abstract: The present invention relates to: a recombinant lentiviral vector comprising a gene encoding a TRAIL protein and a CD protein; and a cell that is transfected with the lentivirus produced by using the vector. A host cell transfected with the recombinant lentivirus of the present invention maintains a high cell proliferation rate and overexpresses a TRAIL protein and a CD protein. Thus, a mesenchymal stem cell transfected with the lentivirus may be usefully employed as a cell therapeutic agent.
    Type: Application
    Filed: February 6, 2017
    Publication date: February 7, 2019
    Applicant: SLBIGEN INC.
    Inventors: Young Chul SUNG, Soon Min LEE, Hey-yon KIM
  • Publication number: 20190043959
    Abstract: An integrated circuit device includes a substrate, a gate structure, a spacer structure, a source/drain region, and a first contact structure. The substrate includes a fin-type active region. The gate structure intersects with the fin-type active region on the substrate, and has two sides and two side walls. The spacer structure is disposed on both side walls of the gate structure and includes a first spacer layer contacting at least a portion of both side walls of the gate structure and a second spacer layer disposed on the first spacer layer and having a lower dielectric constant than a dielectric constant of the first spacer layer. The source/drain region is disposed on both sides of the gate structure. The first contact structure is electrically connected to the source/drain region and includes a first contact plug disposed on the source/drain region and a first metallic capping layer disposed on the first contact plug.
    Type: Application
    Filed: January 15, 2018
    Publication date: February 7, 2019
    Inventors: Joon-Gon Lee, Ryuji Tomita, Chul-Sung Kim, Sang-Jin Hyun
  • Publication number: 20190043839
    Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.
    Type: Application
    Filed: October 4, 2018
    Publication date: February 7, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki Hun YU, Tae Young OH, Nam Jong KIM, Kwang II PARK, Chul Sung PARK
  • Patent number: 10164030
    Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-bum Kim, Chul-sung Kim, Deok-han Bae, Bon-young Koo
  • Publication number: 20180353573
    Abstract: The present invention relates to a pharmaceutical composition comprising an interleukin-7 fusion protein to which an immunoglobulin Fc region has been fused for preventing or treating diseases caused by influenza virus A. The fusion protein comprising the immunoglobulin Fc region and IL-7 according to the present invention protects the body from infection due to influenza virus A and thus can treat diseases which can be caused by the virus.
    Type: Application
    Filed: November 30, 2016
    Publication date: December 13, 2018
    Applicant: GENEXINE, INC.
    Inventors: Moon Cheol KANG, Young Woo CHOI, Donghoon CHOI, Young Chul SUNG
  • Patent number: 10134856
    Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Da-Il Eom, Jeong-Ik Kim, Ja-Hum Ku, Chul-Sung Kim, Jun-Ki Park, Sang-Jin Hyun
  • Publication number: 20180331218
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-lk Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Patent number: 10128245
    Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do Sun Lee, Joon Gon Lee, Na Rae Kim, Chul Sung Kim, Do Hyun Lee, Ryuji Tomita, Sang Jin Hyun
  • Publication number: 20180319858
    Abstract: The present invention relates to a pharmaceutical composition comprising an immunoglobulin Fc region and an IL-7 fusion protein. Specifically, when a fusion protein comprising the immunoglobulin Fc region and IL-7 is administered to an affected area, a strong immune response is induced in the body and thus allows human papillomavirus-caused diseases to be prevented or treated.
    Type: Application
    Filed: December 2, 2016
    Publication date: November 8, 2018
    Applicant: GENEXINE, INC.
    Inventors: Moon Cheol KANG, Young Woo CHOI, Donghoon CHOI, Young Chul SUNG
  • Patent number: 10115702
    Abstract: In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Hun Yu, Tae Young Oh, Nam Jong Kim, Kwang Il Park, Chul Sung Park
  • Publication number: 20180264082
    Abstract: The present invention relates to a method for treating anemia using a long-acting EPO formulation, and more specifically, a method for treating patients with anemia by confirmation of safe, long-acting, and optimal effective dosage and usage in administering a fusion polypeptide which comprises an EPO and an immunoglobulin hybrid Fc to patients with anemia. The method of administering the fusion polypeptide employs an appropriate dosage and usage which not only shows an excellent long-acting property compared to the existing EPO products but also minimizes cardiovascular side effects that may occur due to a rapid increase in hemoglobin level, which is an effect of anemia treatment.
    Type: Application
    Filed: January 8, 2016
    Publication date: September 20, 2018
    Applicants: GENEXINE, INC., GREEN CROSS CORPORATION
    Inventors: Sang-In YANG, Jung-Won WOO, Se Hwan YANG, Young Chul SUNG, Doo Hong PARK, Min Woo KIM
  • Patent number: 10076782
    Abstract: The present invention relates to a metal fiber manufacturing system. The system casts molten metal as a metal fiber; collects the metal fiber in real time; transfers the metal fiber; separates normal products from defective products; and packages a predetermined amount of the normal product metal fiber. The system processes the cast metal fiber continuously or in batches, and manufactures the same, thereby having effects of improving the efficiency of the production process and obtaining significant economic benefits.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: September 18, 2018
    Assignee: POSCO
    Inventors: Un-Kwan Cho, Goo-Hwa Kim, Chul-Sung Jang, Byung-Il Kim
  • Patent number: 10079210
    Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 18, 2018
    Assignee: Samsung Electroics Co., Ltd.
    Inventors: Do-sun Lee, Do-hyun Lee, Chul-sung Kim, Sang-jin Hyun, Joon-gon Lee
  • Publication number: 20180261540
    Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.
    Type: Application
    Filed: August 17, 2017
    Publication date: September 13, 2018
    Inventors: Joon-gon LEE, Ryuji TOMITA, Do-sun LEE, Chul-sung KIM, Do-hyun LEE
  • Patent number: 10067681
    Abstract: A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-sung Park, Joo-sun Choi
  • Patent number: 10043902
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Publication number: 20180178602
    Abstract: Provided is a tire with self-inflation device. The tube is inserted inside the side portion where the extension and contraction movements of the tire are mostly occurring in order to further enhance the efficiency of the air supply to the tire cavity during driving. The air compressed towards the driving direction is injected to the tire cavity, and the air from the outside is charged to the tube due to the negative pressure formed in the tube located in the opposite side of driving. The durability is enhanced by reducing the exposed portion of the regulator.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 28, 2018
    Inventors: Seong Jong PARK, Sang Do NA, Hyoung Seok KIM, In Chul SUNG
  • Publication number: 20180165493
    Abstract: According to various example embodiments, an electronic device is disclosed. The electronic device includes a housing having a first surface facing a first direction and a second surface facing a second, opposing direction. A first area of the first surface includes a plurality of selectable input keys. A second area of the first surface excludes the plurality of keys. A sensor module, such as a fingerprint sensor, is installed to the first area.
    Type: Application
    Filed: November 16, 2017
    Publication date: June 14, 2018
    Inventors: Hwanmyung NOH, Young-Gwon KOO, Taewan KIM, Min-Chul SUNG, Seungwoon LEE
  • Publication number: 20180151556
    Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 31, 2018
    Inventors: Hyo Seok CHOI, Chul Sung KIM, Jae Eun LEE