Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: The present invention relates to a method for diagnosis and screening of cancer by measuring the expression of des-R prothrombin activation peptide fragment F2 (des-R F2) in serum, more precisely, des-R-prothrombin activation peptide fragment F2 which is the protein marker down-regulated specifically in liver cancer, breast cancer, and stomach cancer, and a method for diagnosis and screening of liver cancer, breast cancer, and stomach cancer by quantifying the protein marker. The protein marker of the present invention can be effectively used for diagnosis and screening of liver cancer, breast cancer and stomach cancer by comparing the expression of the said protein marker in a normal subject with that of a liver cancer, breast cancer, or stomach cancer patients.

Abstract: The present invention relates to adenine nucleotide translocator 2 (ANT2) siRNA (small interfering RNA) or ANT2 shRNA (short hairpin RNA) suppressing the expression of ANT2 gene expression and anticancer agent containing the same. Furthermore, the present invention relates to methods for treating breast cancers or stem cells of a breast cancer by treating the same with ANT2 siRNA or ANT2 shRNA. In addition, the invention provides a method for inhibiting metastasis of breast cancer cells with ANT2 siRNA or ANT2 shRNA.

Abstract: A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.

Abstract: There is provided a modulation profile generator and spread spectrum clock generator including the modulation profile generator. The modulation profile generator includes an input signal generator that generates an input signal; a function calculator that outputs a function calculation result in the form of a square root graph by using the input signal as an input of a function; and a profile generator that generates a non-linear modulation profile based on the function calculation result. As a result, it is possible to effectively reduce electromagnetic interference.

Abstract: A color filter substrate for an in-plane switching mode liquid crystal display device includes a first rear side electrode on a first surface of a substrate and formed of a first transparent conductive material including zinc oxide (ZnO) and at least two compounds having second or fourth valence, the first rear side electrode having a first thickness; a black matrix having a lattice shape and a plurality of openings in the lattice shape, the black matrix disposed on a second surface, which is opposite to the first surface, of the substrate; a color filter layer in the plurality of openings; and an overcoat layer on the black matrix and the color filter layer.

Abstract: Provided are a semiconductor package with a reduced lead pitch, and a display panel assembly having the semiconductor package. The semiconductor package includes a film having a hole formed therein, a plating pattern formed under the film and forming a wire; a semiconductor chip placed in the hole and electrically connected to the plating pattern; and a first passivation layer formed at a side opposite to the semiconductor chip about the plating pattern and protecting the plating pattern.

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract: A successive approximation analog/digital converter includes a sample & hold part sampling and holding an intensity of an analog input signal using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of an MSB of a digital value to be converted according to the comparison result of the second comparator and values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the

Abstract: There is provided a modulation profile generator and spread spectrum clock generator including the modulation profile generator. The modulation profile generator includes an input signal generator that generates an input signal; a function calculator that outputs a function calculation result in the form of a square root graph by using the input signal as an input of a function; and a profile generator that generates a non-linear modulation profile based on the function calculation result. As a result, it is possible to effectively reduce electromagnetic interference.

Abstract: A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.

Abstract: A multi-layer printed circuit board (PCB) and a method for fabricating the same are provided. The multi-layer printed circuit board may include a first film and a first insulation layer. The first film may include a first via therein and the first film may further include a first conductive pattern on an upper surface thereof and the first conductive layer may be electrically connected to the first via. The first insulation layer may be on the upper surface of the first film and the first insulation layer may include a second via therein and a second conductive pattern on an upper surface thereof and the second conductive pattern may be electrically connected to the second via. The second via may be electrically connected to the first conductive pattern.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer.

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract: The present invention relates to adenine nucleotide translocator 2 (ANT2) siRNA (small interfering RNA) or ANT2 shRNA (short hairpin RNA) suppressing the expression of ANT2 gene expression and anticancer agent containing the same. Furthermore, the present invention relates to methods for treating breast cancers or stem cells of a breast cancer by treating the same with ANT2 siRNA or ANT2 shRNA. In addition, the invention provides a method for inhibiting metastasis of breast cancer cells with ANT2 siRNA or ANT2 shRNA.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: The present invention provides a method for measuring the temperature of a motor for a hybrid electric vehicle. In preferred embodiments, the method of the present invention can preferably ensure the stability and reliability of motor control by extending the linearity of a temperature sensor attached to the motor within a required measurement range. The present invention preferably provides a method for measuring the temperature of a motor for a hybrid electric vehicle, in which a required measurement range of motor temperature is divided into high and low temperature ranges and a hardware gain circuit is divided into first and second gain blocks such that the first gain block measures the temperature of the high temperature range and the second gain block measures the temperature of the low temperature range.

Abstract: A successive approximation analog/digital converter includes a sample & hold part sampling and holding an intensity of an analog input signal using a single clock cycle of a clock signal; a first comparator comparing the intensity of the analog input signal with comparison voltages determined according to estimated digital values per clock cycle following an operating clock cycle of the sample & hold part; a second comparator comparing the intensity of the analog input signal with a value equal to ½ of a preset reference voltage in the latter half of the operating clock cycle of the sample & hold part; a successive approximation register determining a value of an MSB of a digital value to be converted according to the comparison result of the second comparator and values of bits successive to the MSB according to the comparison result of the first comparator, and generating the estimated digital values by applying estimated values to undetermined bits; and a digital/analog converter generating the

Abstract: The present invention relates to a circuit and method for detecting a short and a disconnection of a resolver for a Hybrid Electric Vehicle (HEV), which can accurately analyze and detect the fault code of the resolver which detects the speed of a drive motor for an HEV and the angle of a rotator for an HEV. For this, the circuit of the present invention is configured such that resistors for detection of a short/disconnection are connected between output signal terminals of a resolver which are connected to input terminals of an RDC connected to a CPU, and the CPU measures certain voltages, obtained according to voltage division by the resistors for detection of a short/disconnection and pull-up resistors connected between a power source and the output signal terminals, with reference to differential signals which are output signals provided to the RDC through the output signal terminals.