Abstract: A method for outputting internal temperature data in a semiconductor memory device can output, at high speed, relatively accurate temperature data externally, without continuously or periodically driving a temperature sensor. The method for outputting the internal temperature data comprises externally outputting internal temperature data stored in a register in a preceding driving cycle in response to a temperature data request signal; driving a temperature sensor during a predefined time section after the output of the internal temperature data is completed; and storing the internal temperature data obtained from the temperature sensor in the register. Power consumption is reduced and accurate temperature data is output externally within a shorter time.

Abstract: A memory card comprising a die paddle having opposed, generally planar first and second die paddle surfaces and multiple peripheral edge segments. Disposed along and in spaced relation to one of the peripheral edge segments of the die paddle is a plurality of contacts, each of which has opposed, generally planar first and second contact surfaces. An inner body partially encapsulates the die paddle and the contacts, the first contact surface of each of the contacts and the first die paddle surface of the die paddle being exposed in and substantially flush with a generally planar first inner body surface of the inner body. The inner body further defines a generally planar second inner body surface which is disposed in opposed relation to the first inner body surface, the second contact surface of each of the contacts being exposed in the second inner body surface. At least one electronic circuit element is attached to the first die paddle surface and electrically connected to at least one of the contacts.

Abstract: An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.

Abstract: A semiconductor memory device includes a semiconductor chip including a first voltage generating circuit that generates a first voltage in response to a first operation control signal, a second voltage generating circuit that generates a second voltage in response to a second operation control signal, a first operation control circuit that generates the first operation control signal, a second operation control circuit that generates the second operation control signal, a first bonding pad connected to an output of the fist voltage generating circuit, and a second bonding pad connected to an output of the second voltage generating circuit. A packaging substrate includes a first substrate pad connected to the first bonding pad and a second substrate pad connected to the second bonding pad. The first and second substrate pads are connected to each other through the packaging substrate.

Abstract: An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.

Abstract: A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.

Abstract: The present invention relates to a liquid crystal display device with a source driver in which a significant signal delay is not generated, and which has a fast response speed. The present invention also provides a liquid crystal display device comprising a scan driver including a D/A converter for outputting analog signals corresponding to gradation data input, a triangular wave generator for outputting triangular wave signals, and a comparator for applying data voltage to each pixel which include OCB liquid crystal cells by comparing the analog signals with the triangular wave signals. The data voltage is a PWM pulse with a varied voltage width.

Abstract: The present invention relates to a liquid crystal display device with a source driver in which a signal without a significant delay is generated, which has a fast response speed and provides a liquid crystal display device having a scan driver comprising a memory in which gradation data values are stored in a lookup table and which sequentially outputs a plurality of switching signals corresponding to the gradation data inputted The device also includes a switching part to which the plurality of switching signals are applied to sequentially select a plurality of voltage levels so that a plurality of pulse waveforms corresponding to the selected plurality of voltage levels are sequentially applied to the respective pixels including liquid crystal cells during one frame, wherein the liquid crystal display further includes a voltage generation part for producing the plurality of voltage levels, the memory outputs a switching signal for resetting the liquid crystal cells in the early stage of each frame, and the

Abstract: A method for outputting internal temperature data in a semiconductor memory device can output, at high speed, relatively accurate temperature data externally, without continuously or periodically driving a temperature sensor. The method for outputting the internal temperature data comprises externally outputting internal temperature data stored in a register in a preceding driving cycle in response to a temperature data request signal; driving a temperature sensor during a predefined time section after the output of the internal temperature data is completed; and storing the internal temperature data obtained from the temperature sensor in the register. Power consumption is reduced and accurate temperature data is output externally within a shorter time.

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract: A liquid crystal display (LCD) device and a method of operating the same prevents a tearing effect from occurring. The LCD device includes a frame memory for writing new red, green and blue data or reading previously written red, green and blue data according to address designation, and a detector which outputs a cut off signal for cutting off operation of a light source controller or a gradation voltage generating portion when the new red, green and blue data are written to the frame memory before the written red, green and blue data are read from the frame memory.

Abstract: A Liquid Crystal Display (LCD) device having an Optically Compensated Bend (OCB) mode, which can restrict an initial high current while supplying a high voltage to a liquid crystal, includes: pixel circuits formed at crossing points of a plurality of scan lines and a plurality of data lines and including an Liquid Crystal (LC) capacitor of an OCB mode formed between a pixel electrode and a common electrode; an Electrostatic Discharge (ESD) protection circuit connected to each data line to prevent static electricity from accumulating in each pixel circuit; a DC-DC converter outputting a voltage for initial bend transition of the LC capacitor of the OCB mode; and a high voltage supplying circuit receiving a voltage of the DC-DC converter and transmitting a high voltage to the common electrode.

Abstract: An LCD and a driving method thereof. A plurality of scan lines are divided into first-group scan lines and second-group scan lines. A scan signal is sequentially applied to the first-group scan lines in a first direction, and a scan signal is then sequentially applied to the second-group scan lines in a second direction. The first group includes odd scan lines and the second group includes even scan lines. Therefore, the brightness difference between the first and last lines can be reduced.

Abstract: A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

Abstract: A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells.

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract: An address coding method, which is performed by a memory device including a plurality of banks each being shared by at least two memory blocks, includes: activating adjacent banks shared by at least two memory blocks during a refresh operation of the memory device, and enabling the refresh operation in each bank alternately between the at least two memory blocks. The method includes activating adjacent banks shared by the at least two memory blocks during another operation of the memory device, and enabling the another operation in each bank alternately between the at least two memory blocks.

Abstract: A memory card comprising a leadframe having at least one die pad, a plurality of contacts, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. The traces are bent in a manner wherein the die pad and the contacts extend along respective ones of spaced, generally parallel frame planes. Disposed on and extending from the die pad and the traces is a plurality of stand-offs. At least one semiconductor die is attached to the die pad and electrically connected to at least one of the traces. A body at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body.

Abstract: A vacuum fluorescent display includes a pair of substrates spaced apart from each other with a predetermined distance. The substrates form a vacuum cell by interposing a side glass. Filaments are mounted within the vacuum cell to emit thermal electrons under the application of voltage. Anode electrodes are formed at one of the substrates, each anode electrode unit having a conductive layer and a phosphor layer formed on the conductive layer. A control electrode surrounds the anode electrode to accelerate or intercept the thermal electrons emitted from the filaments. The control electrode is formed with a single-layered structure.

Abstract: An optic semiconductor package includes a main board of a substantially planar plate shape. The main board includes an aperture therethrough and a plurality of board metal patterns formed at the periphery of the aperture. A package portion is coupled to the main board. The package portion includes a base, a laser diode and a photo detector electrically coupled to the board metal patterns of the main board and bonded to the base. An optical fiber is inserted into the aperture of the main board and disposed adjacent the package portion. The position and tilt of the optical fiber may be adjusted to achieve optimum optical coupling between the optical fiber and the laser diode and the optical fiber and the photo detector. The optical fiber is stably attached to the main board by an adhesive.