Patents by Inventor Chul Woo Park

Chul Woo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CORE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    Publication number: 20120212989
    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
    Type: Application
    Filed: November 28, 2011
    Publication date: August 23, 2012
    Inventors: Hak-Soo YU, Su-A Kim, Hong-Sun Hwang, Chul-Woo Park
  • DATA STORAGE MEDIUM HAVING SECURITY FUNCTION AND OUTPUT APPARATUS THEREFOR
    Publication number: 20120210054
    Abstract: Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus.
    Type: Application
    Filed: October 21, 2010
    Publication date: August 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Jung Kim, In-Kyeong Yoo, Ho-Jung Kim, Chul-Woo Park
  • Semiconductor device having architecture for reducing area and semiconductor system including the same
    Patent number: 8238148
    Abstract: A semiconductor device having an architecture for reducing an area is provided. The semiconductor device includes a memory cell array including a plurality of non-volatile memory cells, a plurality of registers each configured to store pre-fetch unit data, and a write driver circuit configured to write pre-fetch unit data sequentially output from the plurality of registers to the memory cell array during a write operation. The semiconductor device also includes a sense amplifier circuit configured to sense and amplify pre-fetch unit data sequentially output from the memory cell array and to sequentially store the amplified pre-fetch unit data in the plurality of registers, respectively, during a read operation.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jung Kim, Chul Woo Park, Sang Beom Kang, Jung Min Lee, Hyun Ho Choi
  • Bi-directional resistive memory devices and related memory systems and methods of writing data
    Patent number: 8228711
    Abstract: A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jung Kim, Chul-Woo Park, Sang-Beom Kang, Hyun-Ho Choi
  • Resistive memory devices, memory systems and methods of controlling input and output operations of the same
    Patent number: 8223529
    Abstract: A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jung Kim, Yeong-Taek Lee, Chul-Woo Park, Sang-Beom Kang
  • Semiconductor memory devices with mismatch cells
    Patent number: 8199592
    Abstract: A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: June 12, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Young Kim, Chul-Woo Park, Ki-Whan Song
  • MULTI BAND ANTENNA WITH MULTI LAYERS
    Publication number: 20120139796
    Abstract: A multi-layer multi band antenna is provided. Because the antenna carrier has a structure stacked in a plurality of layers having different dielectric constants, the antenna maintains a small size yet has an improved radiation performance in a desired bandwidth.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 7, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chul Woo PARK, Yong Sup Kim, Youngoo Yang
  • SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS
    Publication number: 20120106281
    Abstract: A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 3, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sua KIM, Chul-woo PARK, Hong-sun HWANG, Hak-soo YU
  • RESISTIVE MEMORY DEVICES, INITIALIZATION METHODS, AND ELECTRONIC DEVICES INCORPORATING SAME
    Publication number: 20120099364
    Abstract: A resistive memory device and method of initialization are provided. The resistive memory device includes a first group of resistive memory cells connected between bit lines and a first plate and a second group connected between bit lines and a second plate. First and second initialization voltages are respectively applied to the first and second plates outside a normal path associated with a normal operation of the resistive memory cells.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul Woo Park, In Gyu Baek, Dong Hyun Sohn, Hong Sun Hwang
  • MEMORY CIRCUITS, SYSTEMS, AND MODULES FOR PERFORMING DRAM REFRESH OPERATIONS AND METHODS OF OPERATING THE SAME
    Publication number: 20120099389
    Abstract: A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.
    Type: Application
    Filed: September 20, 2011
    Publication date: April 26, 2012
    Inventors: Chul-woo PARK, Young-hyun Jun, Joo-sun Choi, Hong-sun Hwang
  • SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING
    Publication number: 20120087177
    Abstract: A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 12, 2012
    Inventors: Sua KIM, Chul-Woo Park, Hong-Sun Hwang, Hak-Soo Yu
  • SEMICONDUCTOR MEMORY DEVICE HAVING STACKED STRUCTURE INCLUDING RESISTOR-SWITCHED BASED LOGIC CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20120063194
    Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-gyu BAEK, Hong-sun HWANG, Hak-soo YU, Chul-woo PARK
  • RESISTIVE MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION OF RESISTIVE MEMORY DEVICE
    Publication number: 20120063196
    Abstract: A resistive memory device comprises a memory cell array comprising a plurality of memory units. The memory device performs a refresh read operation to check a condition of each of the memory units. Then, it determines whether to refresh each memory unit based on data read by performing the refresh read operation, and refreshes the memory unit according to a result of the determination. The refresh read operation uses a reference resistance with a smaller margin from a resistance distribution than a normal read operation.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 15, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho Jung Kim, Sang Beom Kang, Hong Sun Hwang, Chul Woo Park
  • Display device having a white light source and a dichroic layer
    Patent number: 8120241
    Abstract: A display device includes a substrate, a white light source on the substrate, a dichroic layer between a viewing surface of the display device and the white light source, the dichroic layer being configured to allow light of a predetermined wavelength band to be transmitted therethrough, and a ΒΌ wavelength layer between the dichroic layer and the white light source.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: February 21, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Joon-Gu Lee, Young-Woo Song, Kyu-Hwan Hwang, Jong-Seok Oh, Jae-Heung Ha, Chul-Woo Park, Jong-Hyuk Lee
  • Multi-level nonvolatile memory device with fast execution of program speed and programming method of the same
    Patent number: 8111563
    Abstract: A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jung Kim, Sang-Beom Kang, Chul Woo Park, Hyun Ho Choi
  • Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers
    Patent number: 8054665
    Abstract: A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-eon Ahn, Ho-jung Kim, Chul-woo Park, Sang-beom Kang, Hyun-ho Choi
  • Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices
    Patent number: 8050074
    Abstract: A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jung Kim, Chul-woo Park, Sang-beom Kang, Jong-wan Kim, Hyun-ho Choi, Young-pil Kim, Sung-chul Lee
  • Memory device, memory system having the same, and programming method of a memory cell
    Patent number: 8031517
    Abstract: A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Jung Kim, Chul Woo Park, Sang Beom Kang, Hyun Ho Choi, Seung Eon Ahn
  • STACKED MEMORY DEVICE AND METHOD OF FABRICATING SAME
    Publication number: 20110228582
    Abstract: A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.
    Type: Application
    Filed: February 10, 2011
    Publication date: September 22, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Woo PARK, Hong-Sun HWANG, In-Gyu BAEK, Dong-Hyun SOHN
  • STACKED SEMICONDUCTOR MEMORY DEVICE AND RELATED ERROR-CORRECTION METHOD
    Publication number: 20110231735
    Abstract: A stacked semiconductor memory device comprises an error correction code (ECC) controller that controls the number of bits in an ECC word and corrects errors in memory cell array layers using the ECC word.
    Type: Application
    Filed: January 28, 2011
    Publication date: September 22, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Woo PARK, Hong-Sun HWANG, Kwan-Young OH, Sang-Beom KANG