Patents by Inventor Chul-Ho Shin

Chul-Ho Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11123880
    Abstract: A robot and an operating method thereof are provided. The robot includes a controller, a force sensor configured to be electrically connected to the controller, mounted in the robot, and sense an external force applied to the robot, an arm configured to be electrically connected to the controller so that an operation is controlled by the controller, an adsorber configured to adsorb a target object, and a coupler configured to couple the arm and the adsorber. The robot may transmit or receive a wireless signal on a mobile communication network constructed according to the 5G (generation) communication.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 21, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Chul Ho Shin, Chang Eui Shin
  • Publication number: 20210060797
    Abstract: A robot and an operating method thereof are provided. The robot includes a controller, a force sensor configured to be electrically connected to the controller, mounted in the robot, and sense an external force applied to the robot, an arm configured to be electrically connected to the controller so that an operation is controlled by the controller, an adsorber configured to adsorb a target object, and a coupler configured to couple the arm and the adsorber. The robot may transmit or receive a wireless signal on a mobile communication network constructed according to the 5G (generation) communication.
    Type: Application
    Filed: October 17, 2019
    Publication date: March 4, 2021
    Applicant: LG Electronics Inc.
    Inventors: Chul Ho Shin, Chang Eui Shin
  • Publication number: 20210052770
    Abstract: The present invention relates to a composition for bone grafting, comprising nucleic acids, a bone graft material, and a cationic polymer, and a bone graft kit for manufacturing the same. The composition for bone grafting, of the present invention, has been confirmed to promote the formation of a cushioning force that can respond to physiological stress and the formation of new bones at grafted sites, and has been confirmed to improve bone grafting convenience, and thus is expected to be effectively usable in the treatment of bone diseases.
    Type: Application
    Filed: January 28, 2019
    Publication date: February 25, 2021
    Applicant: PHARMARESEARCH PRODUCTS CO., LTD.
    Inventors: Ik Soo KIM, Chul Ho SHIN, Min Hyeong PARK, Su Yeon LEE, Tae Gyun KIM, Sung Oh LEE, Han Sol SEO, Byoung Hwan KONG, Jeong Kuk LEE
  • Patent number: 8986554
    Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-sung Kim, Kyoung-seon Kim, Jae-woo Nam, Chul-ho Shin, Shi-young Yi
  • Patent number: 8946089
    Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Kim, Jae-Woo Nam, Chul-Ho Shin, Shi-Yong Yi
  • Patent number: 8900468
    Abstract: A method includes forming a hydrophilic guide layer, a DBARC layer and a photoresist film. A portion of the photoresist film and DBARC layer is exposed to form exposed and unexposed portions. The unexposed photoresist film is removed to form a photoresist pattern including the exposed photoresist film portion. A neutral layer is formed on the photoresist pattern. The photoresist pattern and the DBARC layer of the exposed portion are removed to form first opening portions exposing the guide layer. A block copolymer layer includes a block copolymer having first and second polymer blocks coated on the neutral layer while filling the first opening portions. The block copolymer layer is microphase separated to form a pattern layer including first and second patterns. A pattern including one polymer block is removed to form a pattern mask. The object layer is etched to form a pattern including second opening portions.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Kim, Jae-Woo Nam, Chul-Ho Shin, Shi-Yong Yi
  • Publication number: 20140299889
    Abstract: A semiconductor device includes a first gate structure on a first region of a substrate and a second gate structure on a second region of the substrate, a first impurity region on an upper portion of the substrate adjacent to the first gate structure and a second impurity region on an upper portion of the substrate adjacent to the second gate structure, a first metal silicide layer on the first impurity region, a Fermi level pinning layer on the second impurity region, a second metal silicide layer on the Fermi level pinning layer, and a first contact plug on the first metal silicide layer and a second contact plug on the second metal silicide layer. The Fermi level pinning layer pins a Fermi level of the second metal silicide layer to a given energy level.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 9, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Choong-Rae CHO, Dae-Keun KANG, Eun-Sung KIM, Chul-Ho SHIN, Han-Geun YU
  • Patent number: 8790976
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Publication number: 20140193976
    Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 10, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Sung KIM, Jae-Woo NAM, Chul-Ho SHIN, Shi-Yong YI
  • Patent number: 8715472
    Abstract: A substrate processing method may include forming a plasma; extracting ions from the plasma and accelerating the ions to have uniform or substantially uniform directivity using a grid system; irradiating the ions at a reflector, wherein the reflector includes a plurality of reflecting plates each having a metal plate and an insulating layer on the metal plate, wherein the reflecting plates are parallel or substantially parallel such that the insulating layers are exposed to the ions; reflecting the ions incident on the reflecting plates away from the insulating layers of the reflecting plates; colliding the ions reflected away from the insulating layers with the metal plates to convert the ions into neutral beams; and irradiating the neutral beams onto a substrate to process the substrate.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Wook Hwang, Chul-Ho Shin
  • Publication number: 20140061154
    Abstract: A method includes forming a hydrophilic guide layer, a DBARC layer and a photoresist film. A portion of the photoresist film and DBARC layer is exposed to form exposed and unexposed portions. The unexposed photoresist film is removed to form a photoresist pattern including the exposed photoresist film portion. A neutral layer is formed on the photoresist pattern. The photoresist pattern and the DBARC layer of the exposed portion are removed to form first opening portions exposing the guide layer. A block copolymer layer includes a block copolymer having first and second polymer blocks coated on the neutral layer while filling the first opening portions. The block copolymer layer is microphase separated to form a pattern layer including first and second patterns. A pattern including one polymer block is removed to form a pattern mask. The object layer is etched to form a pattern including second opening portions.
    Type: Application
    Filed: May 30, 2013
    Publication date: March 6, 2014
    Inventors: Eun-Sung KIM, Jae-Woo NAM, Chul-Ho SHIN, Shi-Yong YI
  • Publication number: 20130302966
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Publication number: 20130295772
    Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.
    Type: Application
    Filed: December 19, 2012
    Publication date: November 7, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-sung Kim, Kyoung-seon Kim, Jae-woo Nam, Chul-ho Shin, Shi-young Yi
  • Publication number: 20130288482
    Abstract: In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 31, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Nam, Kyoung-Seon Kim, Eun-Sung Kim, Chul-Ho Shin, Shi-Yong Yi
  • Patent number: 8507353
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Patent number: 8318412
    Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tokashiki Ken, Chul-ho Shin, Sang-Kuk Kim, Do-haing Lee, Dong-seok Lee
  • Patent number: 8252655
    Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun-Hee Bai, Chul-Ho Shin, Shin-Hye Kim, Sang-Kuk Kim
  • Publication number: 20120040508
    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
    Type: Application
    Filed: July 22, 2011
    Publication date: February 16, 2012
    Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
  • Publication number: 20110159442
    Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.
    Type: Application
    Filed: August 30, 2010
    Publication date: June 30, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tokashiki Ken, Chul-ho Shin, Sang-Kuk Kim, Do-haing Lee, Dong-seok Lee
  • Publication number: 20110143532
    Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.
    Type: Application
    Filed: May 17, 2010
    Publication date: June 16, 2011
    Inventors: Keun-Hee Bai, Chul-Ho Shin, Shin-Hye Kim, Sang-Kuk Kim