Abstract: The present invention relates to a pharmaceutical composition comprising a novel compound as an active ingredient for prevention or treatment of transplant rejection. The novel compound SD911 of the present invention was identified to repress the migration of immune cells, increase the engraftment and viability of a grafted tissue, and regulate immune cells. In addition, it was found in a kidney transplantation model that the compound restrained human PBMC from suppressing the engraftment and damaging renal tissues and downregulated the expression of the inflammatory cytokine IL-17, with the consequent effective prevention and treatment of transplant rejection.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: A page buffer includes a bit line sensing circuit, a latch, and a main latch for sensing and storing data from a memory cell. The bit line sensing circuit is coupled with the memory cell by a bit line and configured to perform a bit line sensing operation of sensing first data stored in the memory cell. The latch control circuit is coupled with the bit line sensing circuit. The main latch is coupled with the bit line sensing circuit through the latch control circuit and configured to perform a main latch operation of storing the sensed first data. The cache latch is coupled with the main latch and configured to perform a cache latch operation of storing second data stored in the main latch. Wherein a period of time of the cache latch operation overlaps with a period of time of the bit line sensing operation.

Abstract: A page buffer includes a bit line sensing circuit, a latch, and a main latch for sensing and storing data from a memory cell. The bit line sensing circuit is coupled with the memory cell by a bit line and configured to perform a bit line sensing operation of sensing first data stored in the memory cell. The latch control circuit is coupled with the bit line sensing circuit. The main latch is coupled with the bit line sensing circuit through the latch control circuit and configured to perform a main latch operation of storing the sensed first data. The cache latch is coupled with the main latch and configured to perform a cache latch operation of storing second data stored in the main latch. Wherein a period of time of the cache latch operation overlaps with a period of time of the bit line sensing operation.

Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.

Abstract: The present invention relates to a mesenchymal stem cell having immunomodulatory activity and a preparation method therefor and, more specifically, to: a rapamycin-treated mesenchymal stem cell having immunomodulatory activity, which expresses any one or more cell surface factors selected from the group consisting of CCR1, CCR2, CCR3, CCR4, CCR7, CCR9 and CXCR4; a cell therapy composition comprising the mesenchymal stem cell, for preventing or treating immune disorders; and a preparation method for the mesenchymal stem cell having immunomodulatory activity. The rapamycin-treated mesenchymal stem cell having immunomodulatory activity, according to the present invention, has increased expression of IDO, TGF-? and IL-10 which are factors having immunomodulatory activity, has decreased expression of Phospho-mTOR, Rictor and Ractor which are signal transduction factors of mTOR, and has increased expression, in the cell, of autophagic inducer Beclin1, ATG5, ATG7, LC3I or LCII.

Abstract: The present invention relates to a composition for preventing or treating mitochondrial diseases caused by immunosuppressants, and immune diseases, containing metformin and, more specifically, to a composition for treating mitochondrial diseases caused by immunosuppressants, containing metformin; a pharmaceutical composition for preventing or treating immune diseases, containing, as active ingredients, metformin and an immunosuppressant, which is a target of rapamycin inhibitor (mTOR inhibitor); and a pharmaceutical composite formulation for preventing or treating immune diseases, containing, as ingredients, metformin and a mammalian target of rapamycin inhibitor, wherein the metformin and mammalian target of rapamycin inhibitor are administered simultaneously or separately, or administered in a predetermined sequence.

Abstract: Provided is a composition for alleviating nephrotoxicity caused by an immunosuppressive drug, including metformin, and a composition for preventing or treating an immune disease, including the same. Further, the composition provided can be useful in improving a treatment effect on diseases requiring immunosuppression by effectively alleviating a decline in renal function caused due to side effects of conventional immunosuppressive drugs, and can also be useful in preventing or treating organ transplant rejection, autoimmune diseases, inflammatory diseases and the like since various methods of co-administering a conventional immunosuppressive drug and metformin are suggested to reduce nephrotoxic side effects of conventional immunosuppressive drugs and maximize immunosuppressive or immunomodulatory effects.

Abstract: Provided is a composition for alleviating nephrotoxicity caused by an immunosuppressive drug, including metformin, and a composition for preventing or treating an immune disease, including the same. Further, the composition provided can be useful in improving a treatment effect on diseases requiring immunosuppression by effectively alleviating a decline in renal function caused due to side effects of conventional immunosuppressive drugs, and can also be useful in preventing or treating organ transplant rejection, autoimmune diseases, inflammatory diseases and the like since various methods of co-administering a conventional immunosuppressive drug and metformin are suggested to reduce nephrotoxic side effects of conventional immunosuppressive drugs and maximize immunosuppressive or immunomodulatory effects.

Abstract: The present invention relates to a mesenchymal stem cell having immunomodulatory activity and a preparation method therefor and, more specifically, to: a rapamycin-treated mesenchymal stem cell having immunomodulatory activity, which expresses any one or more cell surface factors selected from the group consisting of CCR1, CCR2, CCR3, CCR4, CCR7, CCR9 and CXCR4; a cell therapy composition comprising the mesenchymal stem cell, for preventing or treating immune disorders; and a preparation method for the mesenchymal stem cell having immunomodulatory activity. The rapamycin-treated mesenchymal stem cell having immunomodulatory activity, according to the present invention, has increased expression of IDO, TGF-? and IL-10 which are factors having immunomodulatory activity, has decreased expression of Phospho-mTOR, Rictor and Ractor which are signal transduction factors of mTOR, and has increased expression, in the cell, of autophagic inducer Beclin1, ATG5, ATG7, LC3I or LCII.

Abstract: A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.

Abstract: A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.

Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.

Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.

Abstract: A non-volatile memory device, a method for controlling the same, and a data processing system using the device and method are disclosed, which relates to a technology for controlling operations of a flash memory device. The non-volatile memory device comprises a cell array configured to comprise a plurality of cells coupled between a word line and a bit line; a drive controller configured to calculate a constant value corresponding to variation in word-line resistance values measured at individual word-line positions, combine the constant value with a word-line address, and set a rising time of the word line; and a voltage provider configured to provide a bias voltage in response to the rising time set in the drive controller.

Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.

Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.

Abstract: A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification voltage applied to a plurality of word lines of the plurality of memory cells until the threshold voltage of the plurality of memory cells is lower than the erase verification voltage, and increasing a voltage level of the erase voltage pulse by an increased voltage level of the erase verification voltage and applying the erase voltage pulse to the plurality of memory cells.

Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.