Abstract: A transparent panel and a display device are provided. The transparent panel includes a substrate, a touch sensing module, and an organic photovoltaic module. The substrate has a first surface and a second surface opposite to the first surface. The touch sensing module is disposed on the first surface of the substrate. The organic photovoltaic module is disposed on the second surface of the substrate. An average visible transmittance of the transparent panel is greater than 70%.

Abstract: A method for preparing quartz glass with low content of hydroxyl and high purity, includes providing silica powders including hydroxyl groups. The silica powders are dehydroxylated, which includes drying the silica powders at a first temperature, heating the silica powders up to a second temperature and introducing a first oxidizing gas including halogen gas, thereby obtaining first dehydroxylated powders, and heating the first dehydroxylated powders up to a third temperature and introducing a second oxidizing gas including oxygen or ozone, thereby obtaining second dehydroxylated powders. The second dehydroxylated powders are heated up to a fourth temperature to obtain a vitrified body. The vitrified body is cooled to obtain the quartz glass with low content of hydroxyl and high purity. The quartz glass prepared by the above method has low content of hydroxyl and high purity. A quartz glass with low content of hydroxyl and high purity is also provided.

Abstract: A server information handling system is secured by a bezel that couples to an access location, such as an air vent at a front or rear face of a housing. The bezel includes a security structure having a lock and configured to couple directly at the front face or with a bezel extension at the rear face so that the server information handling system can use the same bezel with both a front face or rear face rack mount. The bezel has a lock integrated with the security structure, an air filter that fits over the security structure to filter air flowing into the housing, and a filter brace that captures the air filter by coupling to the security structure over the air filter. The filter brace attaches and detaches at the security structure when the security structure locks a server information handling system housing so that the air filter can be changed while the housing remains secure.

Abstract: A user equipment (UE) includes one or more non-transitory computer-readable media containing computer-executable instructions embodied therein, and at least one processor coupled to the one or more non-transitory computer-readable media. The at least one processor configured to execute the computer-executable instructions to receive downlink control information (DCI) on a downlink (DL) channel of a non-terrestrial network (NTN), the DL channel reception ending in a first slot, and transmit an uplink (UL) transmission on a UL channel of the NTN in a second slot. The second slot is separate from the first slot by a timing offset, where a duration of the timing offset is dependent on a type of the UL transmission and a numerology of the UL transmission.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: An RF fingerprint signal processing device configured for executing a machine learning algorithm on a plurality of input signals. The RF fingerprint signal processing device includes a receiver-feature determination circuit and a classifying determination circuit. The receiver-feature determination circuit is configured to compute on the plurality of input signals in a neural network. The classifying determination circuit is coupled with the receiver-feature determination circuit, and the classifying determination circuit is configured to send feedback information of a receiver-feature component to the receiver-feature determination circuit. The receiver-feature determination circuit decreases the receiver-feature weight of the neural network. The receiver-feature weight is associated with the receiver-feature component, and the receiver-feature weight which is decreased is applied for computing an output value of the neural network.

Abstract: An expansion card support device includes an arm configured to rotate between a closed position and an open position relative to an interior surface of a computer housing opposite from one or more interface buses. The arm is substantially parallel to the interior surface in the closed position and substantially perpendicular to the interior surface in the open position. The arm is sized so as to abut edges of one or more expansion cards retained in the one or more interface buses with the arm in the open position. The device further includes a first spring configured to rotate the arm from the closed position to the open position. The device further includes a latch configured to maintain the arm in the closed position with the latch in a latched state.

Abstract: A fuse device may include a PPTC body; a first electrode, disposed on a first side of the PPTC body; and a second electrode, disposed on a second side of the PPTC body. The PPTC body may comprise a polymer matrix and a conductive filler, wherein the fuse device has a trip temperature of less than 120° C.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: Example implementations relate to computing device locations and computing devices having audio components thereon that change operational states. In some examples, a non-transitory computer-readable storage medium can include instructions that when executed cause a processor of an electronic device to determine a default host computing device of a plurality of computing devices, request a location of a first computing device of the plurality of computing devices using a sensor of the default host computing device, and request a location of a second computing device of the plurality of computing devices using the sensor. The instructions when executed can cause the processor to determine a first audio loop potential associated with the first computing device and a second audio loop potential associated with the second computing device, assign the first computing device as an active client and assign the second computing device as an inactive client.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: The present invention provides a chip including an I/O pin and an ESD protection circuit. The ESD protection circuit includes a P-type device and a first diode, wherein the P-type device is coupled between the I/O pin and a ground voltage, and an anode of the first diode is directly connected to the I/O pin. In addition, the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: A k-cluster residue number system has a processor and a memory. The processor is used to generate an addition and subtraction look-up table and a multiplication look-up table based on periodic behaviors of the modulo to compress the sizes of the addition and subtraction look-up table and the multiplication look-up table. The addition and subtraction look-up table has 2mi cells for recording values from zero to (mi?1) in an ascending order twice, wherein mi is a coprime integer of a modular set of the k-cluster residue number system. The multiplication look-up table has S cells, where S = ( m i 2 - 1 4 ) .

Abstract: A k-cluster residue number system has a processor and memory coupled to the processor. The processor is used to generate a modular set composed of P coprime integers, generate a dynamic range by taking a product of the P coprime integers, generate quotient indices for all integers in the dynamic range, generate row indices for all integers in the dynamic range, generate column indices for all integers in the dynamic range, and generate a look-up table according to the quotient indices, row indices, the column indices, and all integers in the dynamic range. P is an integer greater than 2, and the P coprime integers include 2. The memory is used to store the look-up table.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.