Patents by Inventor Chun-An Huang

Chun-An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11933999
    Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: March 19, 2024
    Assignee: Coretronic Corporation
    Inventors: Wen-Chun Wang, Chih-Jen Tsang, Chung-Wei Huang
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240088224
    Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20240090053
    Abstract: In one example in accordance with the present disclosure, an electronic device is described. The electronic device includes a wireless controller. The wireless controller is to establish a first wireless connection between the electronic device and a peripheral device to receive a unique identifier for a second electronic device. The wireless controller is also to establish, based on the unique identifier for the second electronic device, a second wireless connection between the electronic device and the second electronic device. The electronic device includes a wireless transceiver to wirelessly transfer data to the second electronic device through the second wireless connection.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 14, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chung-Chun Chen, Chen-Hui Lin, Chih-Ming Huang, Ming-Shien Tsai
  • Publication number: 20240084370
    Abstract: The disclosure provides a kit for detecting microsatellite instability and a method therefor. The kit includes a negative control, a plurality of qPCR reaction solutions, a qPCR premix and a sterile enzyme-free water; the plurality of qPCR reaction solutions includes 6 pairs of upstream primers and downstream primers of which the MSI mutation site is amplified, and a reference probe for the internal reference and a detection probe for the mutation site. The difference between the amplification of the gene and the gene at the mutation site of the samples and the negative control is used to detect the microsatellite instability. The method and kit as provided is easy and simple without the need of normal tissues being a control, and the need to open the cap. By doing so, aerosol pollution is avoided and sample supplies are conserved.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 14, 2024
    Inventors: Chun MENG, Jing HONG, Liang GUO, Wenxiao MA, Yiwei HUANG, Xiaodie LIN, Liling XIE, Xiaoya WANG, Qixin LIN
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240079277
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, an isolation layer, a gate stack structure, and a dielectric layer. The method includes partially removing the gate stack structure to form a first trench in the gate stack structure. The method includes forming an isolation structure in the first trench. The method includes removing the first gate stack and the second gate stack to form a first recess and a second recess in the dielectric layer. The method includes forming an n-type gate stack and a p-type gate stack in the first recess and the second recess respectively. The method includes forming a conductive line over the n-type gate stack, the p-type gate stack, and the isolation structure. The conductive line electrically connects the n-type gate stack to the p-type gate stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wang-Chun HUANG, Pei-Yu WANG
  • Publication number: 20240079434
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 7, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung, Yu-Chun Chen
  • Publication number: 20240079263
    Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.
    Type: Application
    Filed: February 22, 2023
    Publication date: March 7, 2024
    Inventors: Kai-Hung HSIAO, Chi-Chung JEN, Yu-Chun SHEN, Yuan-Cheng KUO, Chih-Hsiung HUANG, Wen-Chih CHIANG
  • Publication number: 20240076105
    Abstract: A sunken-type cup lid, for covering on a cup mouth of a cup body, according to the present invention is disclosed herein, and comprises: a covering panel, a leaning-on portion and a camber-holding portion. On the covering panel, a sunken-type dome structure is formed to expand a contacting area, from the leaning-on portion laterally and tightly fitting against inside the cup body, to the camber-holding portion downwardly and tightly fitting overneath the cup mouth, so as to be in a multi-directional tight fit manner between the cup lid and the cup body. Thus, it can decrease a liquid-leakage probability incurred between the cup lid and the cup body, and an accidentally detaching probability of the cup lid away from the cup body.
    Type: Application
    Filed: July 2, 2023
    Publication date: March 7, 2024
    Inventors: CHIEN-KUAN KUO, CHUN-HUANG HUANG
  • Publication number: 20240080675
    Abstract: A method for performing network control in a wireless communications system and associated apparatus are provided. The method may include: carrying a set of link information in a preamble of a first data transmission frame transmitted from the first network device to a second network device, wherein the set of link information may include at least one indication among the following indications: a destination device indication, a device assignment indication and a transmission power control indication; wherein a third network device is arranged to monitor wireless transmission in the wireless communications system to obtain the set of link information from the first data transmission frame, and determine spatial reuse (SR) transmission availability of the third network device based on the set of link information.
    Type: Application
    Filed: August 4, 2023
    Publication date: March 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hsin-Chun Huang, Po-Chun Fang, Tsung-Jung Lee, Ray-Kuo Lin
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 11924410
    Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: generate an inter-prediction block for a current block of video data; generate an intra-prediction block for the current block of video data; generate a final prediction block for the current block of video data from the inter-prediction block and the intra-prediction block, including performing each of combined inter/intra prediction (CIIP) mode, overlapped block motion compensation (OBMC), and luma mapping with chroma scaling (LMCS) while generating the final prediction block; and decode the current block of video data using the final prediction block. To generate the final prediction block, the processors may perform LMCS on a first inter-prediction sub-block, combine the LMCS-mapped first inter-prediction sub-block with the intra-prediction block using CIIP, and perform OBMC between the first CIIP prediction block and a second inter-prediction sub-block.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Han Huang, Yao-Jen Chang, Vadim Seregin, Chun-Chi Chen, Marta Karczewicz
  • Patent number: 11923394
    Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Huang, Jiech-Fun Lu, Yu-Chun Chen
  • Patent number: 11920996
    Abstract: A pressure sensor array can be used to record a pressure distribution in gait analysis and/or tactile sensing applications. The pressure sensor array can include a piezo-resistive material and a uniform distribution of a plurality of flexible circuits. Each of the plurality of flexible circuits comprise at least one wire connecting an internal portion of a respective flexible circuit to a common port. A device housing the pressure sensor array can be customized to a size and used for a gait analysis and/or tactile sensing application. The arrangement of the wiring permits partial sensors to be used as part of the pressure sensor array during the gait analysis and/or tactile sensing application.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 5, 2024
    Assignee: CASE WESTERN RESERVE UNIVERSITY
    Inventors: Ming-Chun Huang, Diliang Chen
  • Publication number: 20240072459
    Abstract: An electrical connection structure including a first substrate, a first conductive pad, a second substrate, a second conductive pad, at least two through holes and a conductive material. The first conductive pad is disposed on the first substrate and includes a first top surface. The second conductive pad is disposed on the second substrate and includes a second top surface. The at least two through holes pass through the first substrate and expose portions of the second top surface. A portion of the conductive material is disposed within the at least two through holes, and the conductive material electrically connects the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 29, 2024
    Applicant: InnoLux Corporation
    Inventors: Chia-Chun LIU, Hao-Jung HUANG
  • Publication number: 20240069606
    Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 29, 2024
    Applicants: Acer Incorporated, Sinher Technology Inc.
    Inventors: Yi-Ta Huang, Cheng-Nan Ling, Chih-Chun Liu, Yung-Chang Chiang
  • Publication number: 20240071998
    Abstract: A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Li-Hsien Huang, Hsueh-Lung Cheng, Yao-Chun Chuang, Yinlung Lu