Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor, and the transistor includes a gate structure with a bottom surface under the semiconductor surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer is extended beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure. The first conductive region includes a lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: An electromagnetic wave guidance and beam reshaping structure is favorable to incorporate a radiation source antenna into an energy focusing system. The electromagnetic wave guidance and beam reshaping structure includes a substrate, a plurality of metal patterns and a plurality of hollow structures. The substrate includes a central portion and a peripheral portion that surrounds the central portion. The plurality of metal patterns are disposed on the central portion. The plurality of hollow structures are disposed in the peripheral portion. The metal patterns are axisymmetrically arranged with respect to a central axis of the substrate, and the hollow structures are axisymmetrically arranged with respect to the central axis of the substrate.

Abstract: Provided herein is a ribonucleic acid (RNA) encoding a spike (S) protein or an immunogenic fragment thereof of a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) comprising at least one non-naturally occurring amino acid mutation. In some embodiments, the S protein is derived from a delta variant. Additionally provided are relevant polynucleotides, vectors, cells, compositions, kits, production methods and methods of use.

Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element. Wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region. Wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: An input device, such as a stylus, can include adjustment capabilities that changes a size, shape, stiffness, or other characteristics of a portion of the stylus, such as the tip. The size, shape, stiffness, or other characteristics of a tip of the stylus can be altered to mimic characteristics of a particular writing or drawing tool. For example, the stiffness at the tip, the weight distribution, and/or moment of inertia of a particular tool can be simulated by altering the features of the stylus.

Abstract: A DRAM structure includes a semiconductor substrate, a plurality of DRAM cells, a Bitline, a sense amplifier, and a local wordline. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The Bitline has a first terminal extended along the plurality of DRAM cells to a second terminal, and the Bitline is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the Bitline. The local wordline is connected to a gate terminal of the access transistor of a first DRAM cell in the plurality of DRAM cells. A refresh cycle time, a write cycle time, or a read cycle time of the DRAM structure is less than 5 ns.

Abstract: A semiconductor structure includes a semiconductor substrate, an epitaxy layer, a dielectric layer, a semiconductor layer, a first semiconductor device and a second semiconductor device. The semiconductor substrate has first region and a second region. The epitaxy layer is disposed on and within the first region of the semiconductor substrate. The dielectric layer is disposed on and within the second region of the semiconductor substrate. The semiconductor layer is disposed on the dielectric layer and within the second region. The first semiconductor device is formed on the epitaxy layer. The second semiconductor device is formed on the semiconductor layer.

Abstract: A manufacturing method of an electronic device is provided. The manufacturing method of the electronic device includes a detection step. The detection step is used to detect the pressure distribution of a manufacturing element. The detection step includes: providing a detection element; pressing the manufacturing element on the detection element to generate a plurality of indentation patterns; converting the plurality of indentation patterns into a plurality of image data; using the plurality of image data to calculate an image feature value; and comparing a relationship between the image feature value and a threshold, and generating a comparison result.

Abstract: A composite semiconductor substrate includes a bulk semiconductor substrate and a first well region. The bulk semiconductor substrate has an original semiconductor surface and with a first doping type. The first well region is in the bulk semiconductor substrate with a second doping type, wherein the first doping type is different from the second doping type. There is no PN junction between the bulk semiconductor substrate and the first well region.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support image detail recovery using high frequency and low frequency components of an image frame. In a first aspect, a method of image processing includes receiving image data of an image frame, determining quad phase detection (QPD) image data for the image frame based on the image data for the image frame, and generating a first high frequency component of the image data for a first phase of the image data based on the QPD image data. Other aspects and features are also claimed and described.

Abstract: A compound for degrading a Wee1 protein kinase or a pharmaceutically acceptable salt thereof, and the use thereof in the treatment of proliferative diseases.

Abstract: The present invention provides a single monolithic die comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.

Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

Abstract: A system including a stylus with an inertial measurement unit (IMU) and force/touch/temperature sensors on its sides and/or tip, in some instances in conjunction with force/touch sensors on a tablet computing device or sensors on a watch, is disclosed that obtains measurements such as stylus grip pressure, tilt and touch location, stylus tip pressure, stylus motion, and user temperature. In some instances, these measurements can be obtained through everyday use of the stylus, while in other instances, the user can be prompted to perform certain tasks (e.g., draw specific contours) to assist in data collection. With these measurements, a user profile and baseline profile data can be established and tracked over time, which can include parameters such as tremor amplitude and grip strength. Deviations from baseline profile data can be computed, and when those deviations exceed a threshold, an alert or other wellness insights can be presented to the user.

Abstract: A semiconductor device includes a substrate, a memory component and a heat dissipation component. The memory component is disposed on the substrate. The heat dissipation component is disposed on the substrate. The heat dissipation component has a thermal conductivity greater than that of silicon.