Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.

Abstract: The disclosure provides a method for forming an electrostatic discharge (ESD) protection circuit. The method includes providing a circuit comprising a first voltage supply line, an internal circuit, an input/output (I/O) pad coupling to the internal circuit through a line, and a first ESD protection element between the I/O pad and the internal circuit, wherein the first ESD protection element includes a plurality of first ESD units; and forming a first connection circuit on the first ESD protection element, to couple a first group of the first ESD units to the first voltage supply line though a first node and couple the first group of the first ESD units to the line though a second node.

Abstract: A method to process a diamond composite wafer includes the following steps: (a). forming a plurality of through vias in the diamond composite wafer and a first re-distribution layer on a firs side of the diamond composite wafer; (b). attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer; and (c). releasing the temporary carrier to form a circuit containing diamond composite wafer.

Abstract: A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

Abstract: A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

Abstract: The memory device includes a substrate, a first ball grid array, a first integrated circuit chip, and a first electrostatic discharge protection element. The first ball grid array is disposed on the substrate. The first integrated circuit chip is disposed on the first ball grid array. The first electrostatic discharge protection element is coupled between the second input/output pad of the first integrated circuit chip and the first internal circuit. The first electrostatic discharge protection element is configured to form a first electrostatic discharge path from the second input/output pad to a first voltage supply line. The first electrostatic discharge protection element includes multiple electrostatic discharge units, and at least one of the electrostatic discharge units is free of coupling between the second input/output pad, the first voltage supply line, and the first internal circuit.

Abstract: Systems and techniques are described herein for processing video data. In some examples, a process is described that can include obtaining a plurality of frames, determining a scene cut in the plurality of frames, and determining a smoothed histogram based on the determined scene cut. For instance, the process can include determining a first characteristic of at least a first frame of the plurality of frames and a second characteristic of at least a second frame of the plurality of frames, determining whether a difference between the first characteristic and the second characteristic is greater than a threshold difference, and determining the scene cut based a determination that the difference between the first characteristic and the second characteristic is greater than the threshold difference.