Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A memory circuit includes a column of memory cells configured to receive a set of kth bits of a number H of bits of each input data element of a plurality of input data elements, and each memory cell of the column of memory cells is configured to multiply the kth bit of a corresponding input data element of the plurality of data elements with a first weight data element stored in the memory cell, and to generate a corresponding first product data element. The memory circuit includes an adder tree configured to generate a summation data element based on each of the first product data elements.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

Abstract: A probe card for a circuit probe test system and methods of fabrication thereof. The probe card includes a substrate portion, a guide plate having a plurality of openings, and a plurality of probe pins extending through the openings, including at least one first probe pin configured to carry power between the substrate portion and a device-under-test (DUT), at least one second probe pin configured to electrically couple the DUT to ground, and at least two third probe pins configured to carry loopback test signals between contact regions on the DUT. A low dielectric constant (low-k) material may be located between the third probe pins and the guide plate. The low-k material may prevent direct contact between the third probe pins and the relatively higher dielectric-constant material of the guide plate, which may improve the signal integrity (SI) of the loopback test signals.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: A thermoplastic polyurethane precursor that can be used to prepare a polyurethane having a low initial yellowness index, high yellowing resistance, high thermal oxidative aging resistance, high hydrolysis resistance, and low fisheye.

Abstract: A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

Abstract: An image display device including a first optical element, multiple microlens arrays and a second optical element is provided. The first optical element receives a display image and generates multiple image beams parallel to each other. The microlens arrays respectively receive the image beams, deflect the image beams to generate multiple first light beams, and focuses the first light beams on a first focusing plane. The second optical element is disposed between the first focusing plane and a target area, receives the first light beams, deflects the first light beams to generate multiple second light beams, focuses the second light beams on a second focusing plane, and projects the second light beams to focus on the target area.

Abstract: A projection lens includes a first and a second optical lens assembly. The first optical lens assembly is configured to transmit an image beam to the second optical lens assembly, which projects out the image beam from the projection lens. The second optical lens assembly includes a first and a second reflective element, and an optical member disposed between the first and the second reflective element and including a translucent region and a reflective region. The first reflective element is configured to reflect the image beam from the first optical lens assembly and transmit to the translucent region, which allows the image beam from the first reflective element to pass through and transmit to the second reflective element. The second reflective element is configured to reflect the image beam from the translucent region and transmit to the reflective region, which reflects the image beam from the second reflective element.

Abstract: Behavior report generation monitors the behavior of unknown sample files executing in a sandbox. Behaviors are encoded and feature vectors created based upon a q-gram for each sample. Prototypes extraction includes extracting prototypes from the training set of feature vectors using a clustering algorithm. Once prototypes are identified in this training process, the prototypes with unknown labels are reviewed by domain experts who add a label to each prototype. A K-Nearest Neighbor Graph is used to merge prototypes into fewer prototypes without using a fixed distance threshold and then assigning a malware family name to each remaining prototype. An input unknown sample can be classified using the remaining prototypes and using a fixed distance. For the case that no such prototype is close enough, the behavior report of a sample is rejected and tagged as an unknown sample or that of an emerging malware family.

Abstract: Disclosed herein is the use a cyanobacterial biomass for treating hepatitis B virus (HBV) infection, in particular, chronic HBV infection. According to various embodiments of the present disclosure, the cyanobacterial biomass, upon administration of at least one month, significantly reduces the level of the surface antigen of hepatitis B virus (HBsAg) detectable in the subject receiving the treatment and/or mitigates insomnia associated with chronic HBV infection.

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

Abstract: Provided is a display apparatus including a circuit substrate, a light-emitting layer, a polarizing layer, a quarter waveplate, and a bandpass polarizing reflective layer. The light-emitting layer includes a plurality of first light-emitting structures. The first light-emitting structures have a first peak emission wavelength. The polarizing layer is located on a side of the light-emitting layer away from the circuit substrate. The quarter waveplate is disposed between the polarizing layer and the light-emitting layer and overlaps the light-emitting layer and the polarizing layer. The bandpass polarizing reflective layer is disposed between the quarter waveplate and the light-emitting layer and includes a first bandpass polarizing reflective pattern overlapping the first light-emitting structures. A reflectance of the bandpass polarizing reflective pattern for light with a wavelength in a first wavelength range is greater than 20%. The first wavelength range is the peak emission wavelength ±10 nm.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap.

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

Abstract: Techniques for securing control and user plane separation in mobile networks (e.g., service provider networks for mobile subscribers, such as for 4G/5G networks) are disclosed. In some embodiments, a system/process/computer program product for securing control and user plane separation in mobile networks in accordance with some embodiments includes monitoring network traffic on a mobile network at a security platform to identify an Packet Forwarding Control Protocol (PFCP) message associated with a new session, in which the mobile network includes a 4G network or a 5G network; extracting a plurality of parameters from the PFCP message at the security platform; and enforcing a security policy at the security platform on the new session based on one or more of the plurality of parameters to secure control and user plane separation in the mobile network.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.