Abstract: A projection device includes a light source module, a display panel, a freeform-surface reflective mirror, and a projection lens. The light source module includes a light source, a first Fresnel lens element, and a second Fresnel lens element. The first Fresnel lens element and the second Fresnel lens element are parallel to each other and located between the light source and the display panel. The display panel is arranged between the light source module and the freeform-surface reflective mirror. The projection lens is configured to transmit an image beam out of the projection device, and a direction of an optical axis of the projection lens is different from a direction of a normal of the first Fresnel lens element.

Abstract: A semiconductor package may include a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, and a reinforcement structure mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface of the second semiconductor die, such that the reinforcement structure surrounds less than an entirety of the first semiconductor die and the second semiconductor die. The semiconductor package may include an underfill material formed between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die. The reinforcement structure may include a polymer material located in a space between the first semiconductor die and the second semiconductor die. The polymer material may be a polymer matrix composite having a greater modulus than the underfill material.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

Abstract: A method for beam management performed by a UE is provided. The method includes: receiving a DCI format in a first BWP based on a first QCL assumption specific to the first BWP, the DCI format scheduling a PDSCH reception in a second BWP; receiving an RRC configuration that includes a plurality of candidate TCI states associated with a serving cell in which the PDSCH is scheduled; receiving a MAC CE that indicates a subset of the plurality of candidate TCI states for activation in the second BWP; determining a second QCL assumption specific to the second BWP based on one TCI state in the subset; and receiving the PDSCH in the second BWP based on the second QCL assumption.

Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: An electronic device is provided. The electronic device includes a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer disposed between the first substrate and the second substrate; a plurality of first electrodes disposed between the first substrate and the liquid crystal layer; a plurality of second electrodes disposed between the second substrate and the liquid crystal layer; a first signal line disposed between the first substrate and the liquid crystal layer, and electrically connected to one of the plurality of first electrodes; and a second signal line disposed between the second substrate and the liquid crystal layer, and electrically connected to one of the plurality of second electrodes. The first signal line and the second signal line include a blackened metal.

Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: Provided are an imaging method and system for residual stress of a basin insulator and a method for preparing a test block. The imaging method includes cutting and preparing a standard industrial sample of a basin insulator and testing the acoustoelastic coefficient of the standard industrial sample; then obtaining the residual stress data of the basin insulator and obtaining the spatial point sound velocity distribution of the basin insulator; finally, obtaining a stress distribution cloud map of the basin insulator by calculation of the attribute value and the coordinate data of a to-be-measured location, and performing reliability verification based on the residual stress data.

Abstract: Provided are an intelligent call noise reduction device, method, and headphone. The device includes a first microphone, a second microphone, a sound collecting and processing module and a loudspeaker unit. The first microphone is near to a primary talker sound source. The second microphone is near to a third-party talker sound source. The first microphone receives a talker sound source and generates a first voltage signal based on the talker sound source and receives a background sound source and generates a second voltage signal based on the background sound source. The second microphone receives the talker sound source and generates a third voltage signal based on the talker sound source and receives the background sound source and generates 10 a fourth voltage signal based on the background sound source. The talker sound source includes the primary talker sound source and the third-party talker sound source.

Abstract: A card edge connector includes: a connector base having a card slot and plural terminals; a latch located at one end of the connector base for locking a card; and a releasing member. The releasing member includes two levers and a moving member, the levers are connected with the connector base in a pivoting manner, a first end of the lever is connected with the latch and an opposite second end of the lever is coupled to the moving member, wherein when the card is inserted into the slot and presses against the moving member downwards, the moving member drives the second ends of the levers to move downward, resulting in the first ends moving upwards to push the latch to lock with the card, and when the card is pulled out the moving member resets and drives the levers to release the latch from the card.

Abstract: A medical rehabilitation chair includes a main frame, multiple castor devices mounted on the bottom of the main frame, and two armrest boards mounted on two sides of the main frame. A telescopic damping driver, a seat frame assembly, a backrest frame assembly, a leg support assembly, a lifting mechanism, and a foot support assembly are assembled on the main frame. The seat frame assembly has a front section connecting the leg support assembly and a rear section connecting the backrest frame assembly. The telescopic damping driver drives the backrest frame assembly, the seat frame assembly, and the leg support assembly, to produce different swinging angles. The lifting mechanism drives the seat frame assembly to lift or lower. The foot support assembly is movable in a horizontal direction to protrude from the front section of the main frame.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.