Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150214119
    Abstract: A method includes forming at least two fins of a fin field effect transistor (finFET) on a substrate and forming an insulator layer on the at least two fins. A portion of the insulator layer at a top of a first fin of the at least two fins is removed and a sacrificial layer is formed in a top end of the first fin. The method includes etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins.
    Type: Application
    Filed: January 30, 2014
    Publication date: July 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9093376
    Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • Publication number: 20150206953
    Abstract: A FinFet formed by depositing a thin layer of polycrystalline silicon followed by depositing a stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Freeing space between fins allows stressor films to be deposited closer to the transistor channel, improving the proximity of the stress containing material to the transistor channel and enhancing the stress coupling efficiency by defining a ratio between stress level in the stressor film and stress transferred to the channel for a mobility enhancement. The stress level is enhanced by patterning by removing the n-type workfunction metal from the p-FinFET. After stripping off the soft or hard mask, the p-type workfunction metal is deposited in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Pranita Kerber, Junli Wang, Tanko Yamashita, Chun-chen Yeh
  • Publication number: 20150206877
    Abstract: Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.
    Type: Application
    Filed: March 18, 2015
    Publication date: July 23, 2015
    Inventors: HONG HE, SHOGO MOCHIZUKI, CHIAHSUN TSENG, CHUN-CHEN YEH, YUNPENG YIN
  • Patent number: 9082852
    Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 14, 2015
    Assignees: STMicroelectronics, Inc., GlobalFoundries Inc., International Business Machines Corporation
    Inventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Chun-Chen Yeh
  • Publication number: 20150194496
    Abstract: A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 9, 2015
    Inventors: VEERARAGHAVAN S. BASKER, QING LIU, TENKO YAMASHITA, CHUN-CHEN YEH
  • Publication number: 20150194504
    Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: HONG HE, SHOGO MOCHIZUKI, CHIAHSUN TSENG, CHUN-CHEN YEH, YUNPENG YIN
  • Publication number: 20150194484
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
  • Publication number: 20150194334
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Application
    Filed: March 19, 2015
    Publication date: July 9, 2015
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
  • Patent number: 9076733
    Abstract: A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin, Lei L. Zhuang
  • Publication number: 20150187766
    Abstract: A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A second semiconductor fin is formed on the upper surface of the substrate. The second semiconductor fin extends along the second direction at a second distance to define a second fin width. The second distance may be different with respect to the first distance such that the first and second fin widths are different with respect to one another.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150187867
    Abstract: A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A first gate channel is formed between a first source/drain junction formed in the substrate and a second source/drain junction formed in the first semiconductor fin. A first gate stack is formed on sidewalls of the first gate channel. A first spacer is interposed between the first gate stack and the first source/drain junction.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150187881
    Abstract: A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 2, 2015
    Inventors: VEERARAGHAVAN S. BASKER, QING LIU, TENKO YAMASHITA, CHUN-CHEN YEH
  • Publication number: 20150187914
    Abstract: A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150187577
    Abstract: Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150179766
    Abstract: A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Hui ZANG, Chun-chen YEH, Tenko YAMASHITA, Veeraraghavan BASKER
  • Publication number: 20150179769
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9064901
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: June 23, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9059002
    Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 16, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 9059244
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh