Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double density semiconductor fins and method of fabrication
    Patent number: 9054020
    Abstract: Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Partially isolated Fin-shaped field effect transistors
    Patent number: 9053965
    Abstract: A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin
  • Non-lithographic hole pattern formation
    Patent number: 9054156
    Abstract: A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: June 9, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
  • MAKING AN EFUSE
    Publication number: 20150155238
    Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.
    Type: Application
    Filed: January 29, 2015
    Publication date: June 4, 2015
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Hsueh-Chung Chen, Chiahsun Tseng, Chun-Chen Yeh, Ailian Zhao
  • FINFET WITH MERGE-FREE FINS
    Publication number: 20150144886
    Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 28, 2015
    Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeng Yin
  • Threshold voltage adjustment for thin body MOSFETs
    Patent number: 9040399
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Finfet formed over dielectric
    Patent number: 9041094
    Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    Publication number: 20150140697
    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Jin Cho, Hui Zang
  • REPLACEMENT METAL GATE FINFET
    Publication number: 20150137245
    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • REPLACEMENT METAL GATE FINFET
    Publication number: 20150137244
    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    Publication number: 20150140698
    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Jin Cho, Hui Zang
  • FINFET WITH MERGE-FREE FINS
    Publication number: 20150140762
    Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 21, 2015
    Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeng Yin
  • REPLACEMENT METAL GATE FINFET
    Publication number: 20150137243
    Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • Integrated circuit including DRAM and SRAM/logic
    Patent number: 9018052
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Tenko Yamashita, Chun-Chen Yeh
  • Semiconductor device including ESD protection device
    Patent number: 9012997
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Terence B. Hook, Veeraraghavan S. Basker, Chun-Chen Yeh
  • Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
    Publication number: 20150102453
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
  • Asymmetrical replacement metal gate field effect transistor
    Patent number: 8999795
    Abstract: An asymmetrical field effect transistor (FET) device includes a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, an extended source region disposed on the buried oxide layer and a drain region disposed on the buried oxide layer. The asymmetrical FET device also includes a silicon on insulator region disposed between the extended source region and the drain region and a gate region disposed above the extended source region and the silicon on insulator region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh
  • Integrated circuit including DRAM and SRAM/logic
    Patent number: 8994085
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni, Tenko Yamashita, Chun-Chen Yeh
  • TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    Publication number: 20150076498
    Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicants: Global Foundries, Inc., International Business Machines Corporation
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Jin Cho, Hui Zang
  • NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES
    Publication number: 20150061015
    Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicants: Renesas Electronics Corporation, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Shogo Mochizuki, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin