Patents by Inventor Chun Cheng

Chun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984363
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Publication number: 20240154447
    Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: May 9, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
  • Publication number: 20240153558
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Publication number: 20240155491
    Abstract: Various solutions for low-power wake-up signal (LP-WUS) monitoring with respect to user equipment and network node in mobile communications are described. An apparatus may receive a configuration from a network node. The apparatus may comprise a main radio (MR) and a lower-power wake-up radio (LP-WUR). The apparatus may determine whether to activate or deactivate a low-power wake-up signal (LP-WUS) monitoring by the LP-WUR according to at least one pre-configured condition in the configuration. The apparatus may receive an LP-WUS from the network node via the LP-WUR in an event that the LP-WUS monitoring is activated.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 9, 2024
    Inventors: Chien-Chun Cheng, Wei-De Wu, Yi-Ju Liao, Yi-Chia Lo, Cheng-Hsun Li
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Patent number: 11978720
    Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai Jun Zhan, Chin-Fu Kao, Kuang-Chun Lee, Ming-Da Cheng, Chen-Shien Chen
  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240142794
    Abstract: A stereo projection screen including a scattering screen having a scattering structure layer, a phase retardation layer disposed between the scattering structure layer and the polarized projector, and a metal reflection layer covering at least a part of the scattering structure layer is provided. The scattering structure layer and the phase retardation layer are arranged in a first display area and a second display area of the stereo projection screen. The metal reflection layer is arranged in at least one of the first display area and the second display area. A first image light beam having a first polarization state has a second polarization state after being transmitted to the first display area and leaving the stereo projection screen. A second image light beam having the first polarization state still has the first polarization state after being transmitted to the second display area and leaving the stereo projection screen.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicant: Coretronic Corporation
    Inventors: Chung-Yang Fang, Wen-Chun Wang, Bo-Han Cheng
  • Publication number: 20240145878
    Abstract: An electrode structure of rechargeable battery includes a battery tab stack, an electrode lead, a welding protective layer and a welding seam. The battery tab stack is formed by extension of a plurality of electrode sheets. The electrode lead is joined to one side of the battery tab stack. The welding protective layer is joined to another side of the battery tab stack opposite to the electrode lead. The welding seam extends from the welding protective layer to the electrode lead through the battery tab stack.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kun-Tso CHEN, Tsung-Ying TSAI, Tsai-Chun LEE, Chih-Wei CHIEN, Hui-Ta CHENG
  • Publication number: 20240143083
    Abstract: An interactive simulation system with a stereoscopic image and a method for operating the system are provided. The system includes a three-dimensional display and a control host. The stereoscopic image display is used to display a stereoscopic image. The system includes an interactive sensor that is used to sense gesture of a user or an action that the user manipulates a haptic device so as to produce sensing data. In the meantime, the system detects eye positions of the user. The changes of coordinates with respect to the gesture or the haptic device can be determined and referred to for forming a manipulation track. An interactive instruction can be determined. The stereoscopic image can be updated according to the interactive instruction and the eye positions of the user.
    Type: Application
    Filed: February 15, 2023
    Publication date: May 2, 2024
    Inventors: YUNG-CHENG CHENG, CHUN-HSIANG YANG
  • Publication number: 20240140782
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: PO CHEN YEH, YI-HSIEN CHANG, FU-CHUN HUANG, CHING-HUI LIN, CHIAHUNG LIU, SHIH-FEN HUANG, CHUN-REN CHENG
  • Publication number: 20240142094
    Abstract: A lamp device includes a light-emitting element, a first clamping element, a second clamping element, an outer cover and a counterweight. The first clamping element is connected with the light-emitting element. The outer cover is disposed on the first clamping element. The counterweight is connected to the outer cover and is adjacent to a connection between the first clamping element and the second clamping element. When the lamp device clamps a screen, the second clamping element abuts against a back surface of the screen.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 2, 2024
    Applicant: Qisda Corporation
    Inventors: Pin-Yuan SHENG, Yu-Han CHENG, Pai-Chun CHENG
  • Patent number: 11974302
    Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: April 30, 2024
    Assignee: Hannibal IP LLC
    Inventors: Chien-Chun Cheng, Tsung-Hua Tsai, Yu-Hsin Cheng, Wan-Chen Lin
  • Patent number: 11972957
    Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-chun Yang, Chih-Lung Cheng, Yi-Ming Lin, Po-Chih Huang, Yu-Hsiang Juan, Xuan-Yang Zheng
  • Patent number: 11974367
    Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 30, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
  • Patent number: 11973117
    Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Chang-Ting Chung, Wei-Cheng Lin, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 11973077
    Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11971565
    Abstract: An absorption type near-infrared filter comprising a first multilayer film, a second multilayer film, and an absorption film, wherein in the ultraviolet band, the difference of between the wavelength with the transmittance at 80% of the absorbing film and the wavelength with the reflectivity at 80% of the first multilayer film falls in the range between 25 nm and 37 nm, the difference of between the wavelength with the transmittance at 50% of the absorbing film and the wavelength with the reflectivity at 50% of the first multilayer film falls in the range between 6 nm and 14 nm, and the difference of between the wavelength with the transmittance at 20% of the absorbing film and the wavelength with the reflectivity at 20% of the first multilayer film falls in the range between ?6 nm and 2.5 nm.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 30, 2024
    Assignees: PTOT (SUZHOU) INC., PLATINUM OPTICS TECHNOLOGY INC.
    Inventors: Chung-Han Lu, Hsiao-Ching Shen, Chun-Cheng Hsieh, Ming-Zhan Wang
  • Publication number: 20240133467
    Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 25, 2024
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Yu-Xiang GENG, Chun-Chieh CHEN, Ling-Cheng TSENG, Yi-Wen TSAI, Ching-Yao HUANG
  • Publication number: 20240136316
    Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang