Patents by Inventor Chun-Chieh Chuang
Chun-Chieh Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250133856Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first integrated circuit (IC) die stacked with a second IC die. The first IC die includes a plurality of photodetectors disposed within a first substrate. The second IC die includes a plurality of pixel transistors and a semiconductor capacitor disposed on a second substrate. The semiconductor capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a doped capacitor region. The first capacitor electrode overlies the second substrate and comprises a protrusion disposed in the second substrate. The capacitor dielectric layer is disposed between the first capacitor electrode and the second substrate. The doped capacitor region is disposed within the second substrate and underlies the first capacitor electrode. The plurality of photodetectors, the plurality of pixel transistors, and the semiconductor capacitor define a pixel.Type: ApplicationFiled: October 19, 2023Publication date: April 24, 2025Inventors: Shen-Hui Hong, Chun-Chieh Chuang, Feng-Chi Hung, Jen-Cheng Liu
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Publication number: 20250006762Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.Type: ApplicationFiled: January 12, 2024Publication date: January 2, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh CHUANG, Hsin-Hung CHEN, Wen-I HSU, Peng-Chieh CHIN, Feng-Chi HUNG, Ming-En CHEN, Jen-Cheng LIU, Dun-Nian YAUNG
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Publication number: 20230378139Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: July 26, 2023Publication date: November 23, 2023Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
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Publication number: 20230361085Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first integrated chip (IC) tier and a second IC tier. The second IC tier comprises a second plurality of conductors within a second insulating structure disposed on the second semiconductor body. A conductive pad is electrically coupled to the second plurality of conductors and has a conductive surface available to a side of the second semiconductor body facing away from the first semiconductor body. The IC first tier contacts the second IC tier along a bonding interface including one or more conductive regions and one or more insulating regions. The one or more conductive regions laterally outside of a bottom surface of the conductive pad.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Patent number: 11804473Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.Type: GrantFiled: May 28, 2021Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Patent number: 11798916Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: July 30, 2018Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
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Publication number: 20230201613Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Patent number: 11596800Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: GrantFiled: June 15, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Patent number: 11152414Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth greater than the first depth. The pixel region includes only NMOS devices and the periphery region includes both NMOS and PMOS devices.Type: GrantFiled: January 28, 2019Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Volume Chien
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Publication number: 20210288029Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects arranged within a first inter-level dielectric (ILD) structure on a first substrate, and a second plurality of interconnects arranged within a second ILD structure between the first ILD structure and a second substrate. A bonding structure is disposed within a recess extending through the second substrate. A connector structure is vertically between the first plurality of interconnects and the second plurality of interconnects. The second plurality of interconnects include a first interconnect directly contacting the bonding structure. The second plurality of interconnects also include one or more extensions extending from directly below the first interconnect to laterally outside of the first interconnect and directly above the connector structure, as viewed along a cross-sectional view.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Patent number: 11024602Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.Type: GrantFiled: March 28, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sin-Yao Huang, Chun-Chieh Chuang, Ching-Chun Wang, Sheng-Chau Chen, Dun-Nian Yaung, Feng-Chi Hung, Yung-Lung Lin
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Patent number: 11011567Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: GrantFiled: November 8, 2019Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
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Patent number: 10886320Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.Type: GrantFiled: April 18, 2019Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
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Patent number: 10879297Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.Type: GrantFiled: April 18, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
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Patent number: 10861899Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.Type: GrantFiled: December 20, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
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Publication number: 20200306552Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Patent number: 10682523Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: GrantFiled: October 8, 2018Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Publication number: 20200127027Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
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Publication number: 20200075659Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
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Patent number: 10535697Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: GrantFiled: November 6, 2017Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu