Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract: An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region.

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth. The second depth is greater than the first depth.

Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

Abstract: Embodiments of the invention relate to dual shallow trench isolations (STI). In various embodiments related to CMOS Image Sensor (CIS) technologies, the dual STI refers to one STI structure in the pixel region and another STI structure in the periphery or logic region. The depth of each STI structure depends on the need and/or isolation tolerance of devices in each region. In an embodiment, the pixel region uses NMOS devices and the STI in this region is shallower than that of in the periphery region that includes both NMOS and PMOS device having different P- and N-wells and that desire more protective isolation (i.e., deeper STI). Depending on implementations, different numbers of masks (e.g., two, three) are used to generate the dual STI, and are disclosed in various method embodiments.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: Provided is a method of fabricating an image sensor device. The method includes providing a first substrate having a radiation-sensing region disposed therein. The method includes providing a second substrate having a hydrogen implant layer, the hydrogen implant layer dividing the second substrate into a first portion and a second portion. The method includes bonding the first portion of the second substrate to the first substrate. The method includes after the bonding, removing the second portion of the second substrate. The method includes after the removing, forming one or more microelectronic devices in the first portion of the second substrate. The method includes forming an interconnect structure over the first portion of the second substrate, the interconnect structure containing interconnect features that are electrically coupled to the microelectronic devices.

Abstract: A semiconductor image sensor device includes first and second semiconductor substrates. A pixel array and a control circuit are formed in a first surface of the first substrate. An interconnect layer is formed over the first surface of the first substrate and electrically connects the control circuit to the pixel array. A top conducting layer is formed over the interconnect layer to have electrical connectivity with at least one of the control circuit or the pixel array via the interconnect layer. A surface of a second substrate is bonded to the top conducting layer. A conductive through-silicon-via (TSV) passes through the second substrate, and has electrical connectivity with the top conducting layer. A terminal is formed on an opposite surface of the second substrate, and electrically connected to the TSV.

Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.

Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.

Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region.