Patents by Inventor Chun-Chih Chen

Chun-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892360
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20210004517
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • Patent number: 10879236
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 10879339
    Abstract: A display panel including a first array substrate, a first pad, and a second pad is provided. The first array substrate includes a first substrate, a first active element, a first display element, and a second display element. The first substrate has a top surface and a bottom surface disposed opposite to each other. The first active element is disposed on the top surface of the first substrate. The first display element is disposed on the top surface of the first substrate and is electrically connected to the first active element. The second display element is disposed on the top surface of the first substrate and is disposed separately from the first display element.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 29, 2020
    Assignee: Au Optronics Corporation
    Inventors: Tsung-Ying Ke, Yung-Chih Chen, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu
  • Patent number: 10867823
    Abstract: A fault detection method in a semiconductor fabricating factory is provided. The method includes delivering a test vehicle along a rail to a test region. The method further includes projecting a test signal from a transducer that is positioned on the test vehicle over a check board when the test vehicle is located within the test region. The check board and the test vehicle are arranged along an axis that is parallel to the rail. The method also includes performing an analysis of the test signal projected over the check board. In addition, the method includes issuing a warning alarm when an abnormality is detected based on the analysis result.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Jung Huang, Yung-Lin Hsu, Kuang-Huan Hsu, Wei-Chih Chen, Jen-Ti Wang, Chih-Hung Liu
  • Patent number: 10867990
    Abstract: Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Fu-Chih Yang, Chun Lin Tsai, Yi-Min Chen, Chih-Yuan Chan
  • Patent number: 10867099
    Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10867100
    Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Publication number: 20200376446
    Abstract: A preparation method of separation membrane is provided. First, a polyimide composition including a dissolvable polyimide, a crosslinking agent, and a solvent is provided. The dissolvable polyimide is represented by formula 1: wherein B is a tetravalent organic group derived from a tetracarboxylic dianhydride containing aromatic group, A is a divalent organic group derived from a diamine containing aromatic group, A? is a divalent organic group derived from a diamine containing aromatic group and carboxylic acid group, and 0.1?X?0.9. The crosslinking agent is an aziridine crosslinking agent, an isocyanate crosslinking agent, an epoxy crosslinking agent, a diamine crosslinking agent, or a triamine crosslinking agent. A crosslinking process is performed on the polyimide composition. The polyimide composition which has been subjected to the crosslinking process is coated on a substrate to form a polyimide membrane. A dry phase inversion process is performed on the polyimide membrane.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Textile Research Institute
    Inventors: Shang-Chih Chou, Chun-Hung Chen, Chun-Hung Lin, Kueir-Rarn Lee
  • Patent number: 10854681
    Abstract: A display device includes a pixel circuit substrate, a plurality of light emitting devices, a driver circuit substrate, a plurality of connection terminals, and an electrically conductive adhesion layer. The light emitting devices are electrically connected to the pixel circuit substrate. The driver circuit substrate is disposed on a back side of the pixel circuit substrate. The connection terminals electrically connect the driver circuit substrate to the pixel circuit substrate. The electrically conductive adhesion layer is disposed between the pixel circuit substrate and the driver circuit substrate.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 1, 2020
    Assignee: Au Optronics Corporation
    Inventors: Yung-Chih Chen, Chun-Hsin Liu, Li-Chih Hsu, Tsung-Ying Ke, Wan-Tsang Wang, Keh-Long Hwu, Ya-Ting Hsu
  • Publication number: 20200373267
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 10844477
    Abstract: Sputtering systems and methods are provided. In an embodiment, a sputtering system includes a chamber configured to receive a substrate, a sputtering target positioned within the chamber, and an electromagnet array over the sputtering target. The electromagnet array includes a plurality of electromagnets.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsuan-Chih Chu, Chien-Hsun Pan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20200366212
    Abstract: According to aspects of the disclose, a converter system includes a primary-side circuit configured to be coupled to an energy source, a secondary-side circuit configured to be coupled to a load, the secondary-side circuit including an energy storage device and at least one switching device configured to control a load current provided by the energy storage device to the load, and a controller configured to be coupled to the primary-side circuit and the secondary-side circuit, the controller being further configured to determine a parameter indicative of an energy level of the energy storage device, and control, based on the parameter indicating that the energy level of the energy storage device is below a discharge energy level, the at least one switching device to be in an open and non-conducting position.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Inventors: Pin-Chieh Chan, Huang-Yun Chen, Chun Chih Fu
  • Patent number: 10840592
    Abstract: An electronic device and its antenna assembly are provided. The electronic device includes a display screen, a metal foothold, a motherboard, and an antenna assembly. The display screen and the motherboard are disposed at two opposite surfaces of the metal foothold. The antenna assembly electrically connected to the motherboard includes a metal frame, a plastic sheet, an antenna, and a conductive sheet. The metal frame is disposed at the metal foothold, and one side of the metal frame has an opening, so that the plastic sheet can be embedded in the opening. The antenna includes an antenna main board disposed at the plastic sheet and a double-sided antenna disposed at two opposite sides of the antenna main board. The conductive sheet is connected to the double-sided antenna and lapped over the metal frame.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 17, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Shih-Keng Huang, Ya-Jyun Li, Ching-Hsiang Ko, Chun-Chih Chen
  • Publication number: 20200359499
    Abstract: A flexible display including a buffer layer, a plurality of pixel structures, a plurality of first pads, a plurality of first conductive through holes, a flexible circuit board and an adhesive layer is provided. The pixel structures are disposed on a first surface of the buffer layer. The first pads are disposed on a second surface of the buffer layer. The first conductive through holes are embedded in the buffer layer. The first pads are respectively electrically connected to the pixel structures through the first conductive through holes. The adhesive layer is disposed between the second surface of the buffer layer and the flexible circuit board. An orthogonal projection of the adhesive layer on the buffer layer overlaps an orthogonal projection of the pixel structures on the buffer layer. The first pads are electrically connected to first signal lines of the flexible circuit board.
    Type: Application
    Filed: February 17, 2020
    Publication date: November 12, 2020
    Applicant: Au Optronics Corporation
    Inventors: Keh-Long Hwu, Yung-Chih Chen, Tsung-Ying Ke, Wan-Tsang Wang, Chun-Hsin Liu
  • Patent number: 10825383
    Abstract: A display device including a first substrate, pixel structures, a second substrate, first signal lines, and second signal lines is provided. The pixel structures are disposed on a first surface of the first substrate. Each of the pixel structures includes a switch element and a pixel electrode. The switch element has a first terminal, a second terminal, and a control terminal. The pixel electrode is electrically connected to the second terminal of the switch element. The second substrate is disposed under a second surface of the first substrate. The first signal lines and the second signal lines are disposed on the second substrate. The first terminals and the control terminals of the switch elements of the pixel structures are respectively electrically connected to the first signal lines and the second signal lines, wherein the first signal lines are substantially parallel to the second signal lines.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 3, 2020
    Assignee: Au Optronics Corporation
    Inventors: Li-Chih Hsu, Yung-Chih Chen, Chun-Hsin Liu, Ya-Ting Hsu, Wan-Lin Chen, Wan-Tsang Wang, Tsung-Ying Ke, Keh-Long Hwu
  • Patent number: 10824166
    Abstract: A method of distributing task regions for a plurality of cleaning devices, including: dividing a task map into a plurality of basic sub-regions according to concave corners corresponding to the shape of the task map; combining each two adjacent basic sub-regions, and calculating basic cleaning time corresponding to each of the combined basic sub-regions; repeatedly combining each two adjacent basic sub-regions according to the basic cleaning time, and obtaining a basic partition result; selecting starting blocks according to positions of the plurality of task sub-regions in the basic partitioning result; combining the task sub-regions according to the position of each starting block, the position of each task sub-region, and the cleaning time corresponding to each task sub-region, and obtaining the task region distribution result; enabling cleaning devices to perform cleaning tasks according to the position of each cleaning device and the task region distribution result.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 3, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Tao-Chih Hsu, Yang-Sheng Wang, Chun-Ting Chen, Yu-Ching Chen
  • Patent number: 10817643
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Patent number: 10816989
    Abstract: A method of distributing task areas, adapted to a cleaning device, is provided, including: receiving a task map; obtaining a shape that corresponds to the task map; dividing the task map into a plurality of sub-regions according to a plurality of recesses in the shape; merging the two adjacent sub-regions that have a common long side or short side, and obtaining a plurality of merge results that correspond to each of the merge actions; calculating a plurality of cleaning times for each of the merge results for the cleaning device; selecting the merge result that has the shortest cleaning times as a first distribution result; and enabling the cleaning device to perform a cleaning task according to the first distribution result.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: October 27, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yu-Ching Chen, Tao-Chih Hsu, Yang-Sheng Wang, Chun-Ting Chen
  • Patent number: 10804541
    Abstract: An electrode and a device employing the same are provided. The electrode includes a main body, and an active material. The main body includes a cavity and is made of a conductive network structure. In particular, the active material is disposed in the cavity, wherein the length of the longest side of the particle of the active material is greater than the length of the longest side of the pore of the conductive network structure such that the active material is confined in the conductive network structure.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 13, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuang-Yao Chen, Ting-Wei Huang, Chien-Chih Chiang, Chun-Hsing Wu, Chang-Chung Yang, Wen-Sheng Chang