Abstract: A shift register in an amorphous-silicon gate driver comprises a pull-up transistor and two pull-down modules. The pull-up transistor produces a positive pulse when the clock signal is high and the gate of the pull-up transistor is also high. The gate of the pull-up transistor is pulled down to a negative voltage level Vss by two pull-down transistors in the pull-down modules. Each pull-down module also has a further pull-down transistor to keep the output terminal at Vss after the output pulse is produced. The two pull-down modules are operated in a cooperative manner so that each pull-down transistor is conducting approximately 50% of the time. The gates of the pull-down transistors are kept at a positive voltage level approximately 50% of the time and at Vss? approximately 50% of the time with Vss? being more negative than Vss.

Abstract: A backup shift register module having at least two backup shift registers is used to repair a defective main shift-register module. A normally open link is provided between the input of first backup shift register and the input of each odd-numbered main shift register, and between the output of first backup shift register and the input of each even-numbered main shift register. A normally open link is provided between the input of second backup shift register and the input of each even-numbered main shift register, and between the output of second backup shift register and the input of each odd-numbered main shift register. If one main shift register is defective, the input and output of the defective shift register are disconnected from the cascade link, and the normally open links are connected to the input of the defective shift register and the output of the next shift register are connected.

Abstract: A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

Abstract: Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.

Abstract: A shift register circuit having shift registers comprising a first transistor having a gate and a first source/drain for receiving an output signal of a pre-stage shift register, a second transistor having a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a first clock signal, and a second source/drain coupled to a output, a first pull-down module coupled to the output terminal, for receiving the first clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the first clock signal are at low voltage level, and a second pull-down module coupled to the output and a second clock signal, wherein the output is coupled to a first voltage level when the output signal of pre-stage shift register and the second clock signal are at low voltage level.

Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.