Abstract: A light modulating Backplane with multi-layer pixel electrodes is disclosed. The light modulating backplane includes a multiple pixel control circuits and multiple pixel electrodes. The pixel electrodes include a first pixel electrode layer coupled to a corresponding pixel control circuit and a second pixel electrode layer. A passivation layer covers the pixel electrodes. The first pixel electrode layer is formed using a first metal such as copper and the second pixel electrode layer is formed using a second metal such as aluminum.

Abstract: A see-through near-to-eye viewing optical system, which can be used in a head-mounted augmented reality display system, is provided. The see-through near-to-eye viewing optical system of the present invention comprises an LED illumination system for generating a light and a pre-polarizer for concentrating said light onto a PBS. Then an LCOS panel receives and reflects said light towards a post-polarizer after generating an image. The light travels from the post-polarizer and passes through an eyepiece for magnifying the image, and continues towards a 50/50 beam splitter. Afterwards the beam splitter transmits said light and another light from the outside field of view to user's eyes simultaneously and thus, the user can see what is shown on the glass screen while still being able to see through it.

Abstract: A head up display system comprises an optical projector, a projection screen, a combiner, a driver system board, an event data recorder, a front image sensor and a rear image sensor. The optical projector is a front projector or a rear projector for projecting the image onto the projection screen. Then the combiner projects a virtual image from the image of the projection screen within two to three meters behind the combiner and thus, drivers are able to observe the environment outside the car and to read the information provided by the head up display system simultaneously. The driver system board can connect to a driver's smart phone through wire (such as HDMI/MHL) or wireless (such as WiFi) and thus, an image from real-time contents of the smart phone or an image from other functions of the smart phone can be transmitted to the driver system board and projected by the optical projector for drivers' watch or use.

Abstract: A head-mounted augmented reality display system, comprise: an immersive or see-through type near-to-eye viewing optics; a CMOS image sensor; a sound receiver; an earphone; a driver system board; and a frame. The image sensor and the sound receiver capture the image and record the sound from the outside world to the driver system. By the image and audio processing of the driver system, the generated image outputs to the immersive or see-through type near-to-eye viewing optics, and the generated audio outputs to the ear phone.

Abstract: A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

Abstract: A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

Abstract: An MxN dynamic spare column replacement memory system for storing M N-bit data words includes a random access memory (RAM) formed by a rectangular array of M rows and N+S columns of single-bit memory cells. Each row has a unique address and stores an N-bit word using a selected set of N of its N+S cells. An N-line parallel data bus provides data access to the DRAM. Responding to a switching instruction from a switch controller at the start of each memory access cycle, a crossbar switch selectively connects each of the N lines of the data bus to a separate one of the N+S columns. Thus during a memory read or write access cycle the N data lines access N cells of an addressed row columns. The remaining S cells of the row are unused. A host computer occasionally checks the DRAM for defective memory cells, and upon finding a defective cell or cells in any row, the host stores the row address and a switching instruction in the switch controller.

Abstract: An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

Abstract: An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller.

Abstract: A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data.