Patents by Inventor Chun-Fai Cheng

Chun-Fai Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11329159
    Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Publication number: 20220037196
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Publication number: 20210391225
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Fai CHENG, Chang-Miao LIU, Kuan-Chung CHEN
  • Patent number: 11152250
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 11145536
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 11107736
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Inventors: Chun-Fai Cheng, Chang-Miao Liu, Kuan-Chung Chen
  • Publication number: 20200403098
    Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.
    Type: Application
    Filed: July 14, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Fai CHENG, Ka-Hing FUNG, Li-Ping HUANG, Wei-Yuan LU
  • Patent number: 10872897
    Abstract: A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Publication number: 20200328106
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Publication number: 20200279854
    Abstract: A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Patent number: 10727340
    Abstract: A p-type field effect transistor includes a pair of spacers over a substrate top surface. The p-type field effect transistor includes a channel recess cavity in the substrate top surface between the pair of spacers. The p-type field effect transistor includes a gate stack with a bottom portion in the channel recess cavity. The p-type field effect transistor includes a source/drain (S/D) recess cavity including a bottom surface and sidewalls below the substrate top surface, wherein the S/D recess cavity includes a portion extending below the gate stack. The p-type field effect transistor includes a strained material filling the S/D recess cavity. The p-type field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the bottom surface and sidewalls of the S/D recess cavity. The S/D extension includes a portion between the gate stack and the S/D recess cavity.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Patent number: 10699940
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 10658372
    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Publication number: 20200111700
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 9, 2020
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Publication number: 20200020701
    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Patent number: 10424588
    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Publication number: 20190157135
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 23, 2019
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Publication number: 20190139969
    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Patent number: 9847225
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, An-Shen Chang, Hui-Min Lin, Tsz-Mei Kwok, Hsien-Ching Lo
  • Patent number: RE47562
    Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Bwo-Ning Chen, Chin-Te Su, Huang-Sheng Ho