Abstract: A pMOS transistor having reduced diffusion from source/drain regions and a method of forming the same are provided. The pMOS transistor includes a source/drain region doped with a p-type impurity and a diffusion-retarding material in a semiconductor substrate. The pMOS transistor further includes a gate dielectric over a channel region in the semiconductor substrate, a gate electrode over the gate dielectric, and a lightly doped source/drain (LDD) region substantially aligned with an edge of the gate electrode. The diffusion-retarding material preferably includes carbon, fluorine, nitrogen, and combinations thereof.

Abstract: A method for forming the N-MOS and P-MOS transistor regions of a CMOS device having reduced depletion of the N and P dopants in the polysilicon gate and reduced penetration of the N and P dopants through the oxide layer and into the channel regions of the N-MOS and the P-MOS transistor. The improvements are accomplished by a new implantation treatment of the polysilicon gate layer prior to implanting the polysilicon layer with the N-type dopant and the P-type dopant for purposes of forming the transistor gates. The implantation treatment prior to the N-type dopant and P-type dopant implantation, includes a first implantation of Ge and/or an inert gas and a second implantation of carbon or fluorine.

Abstract: A semiconductor device having well-defined profiles is disclosed. A p-type pocket/halo region is preferably formed along a channel-side border of the heavily doped source/drain region to neutralize diffused n-type elements. A diffusion-retarding region is formed to retard diffusion for both p-type and n-type impurities by substantially overlapping or extending beyond the p-type pocket/halo region and the N+ S/D region at least on the channel side.

Abstract: Methods for rapid thermal processing of semiconductor substrates are provided. An exemplary method comprises directing radiant heat energy emitted from a heat source toward a backside surface of the semiconductor substrate. Systems for rapid thermal processing also are provided.

Abstract: A method of fabricating a stacked gate dielectric layer. First, a semiconductor substrate having a native oxide thereon is provided. Next, a first gas containing hydrogen is introduced on the semiconductor substrate. A nitride is deposited on the native oxide. A second gas containing nitrous oxide is introduced on the semiconductor substrate. A third gas containing nitrogen oxide is introduced on the semiconductor substrate. Finally, an annealing treatment is performed.

Abstract: A method of etching a metal line. A substrate with a metal layer to be etched is provided, on which an amorphous carbon doped layer is formed over the metal layer by plasma enhanced chemical vapor deposition (PECVD). A resist layer is formed over the amorphous carbon doped layer, and the resist layer is patterned to define a resist mask. The amorphous carbon doped layer is etched to define a hardmask, the resist mask is stripped, and the metal layer not covered by the hardmask is etched to form a metal line for forming an interconnect.

Abstract: A method of fabricating a well-filled STI Structure in a semiconductor substrate. A trench is formed in the semiconductor substrate. A liner oxide and a liner nitride are formed on the bottom and sidewall of the trench subsequently. A HDP oxide layer is deposited in the trench conformally to fill a portion of the trench. A layer of poly-silicon is deposited over the HDP oxide layer conformally. The semiconductor substrate is subjected to a thermal treatment to oxidize the poly-silicon. The surface of the semiconductor substrate is planarized to form a shallow trench isolation structure. The trench is well filled by the oxidized poly-silicon and the HDP oxide without voids and seams.

Abstract: A method of etching a low-k dielectric layer. A substrate having a low-k dielectric layer to be etched, on which an amorphous carbon doped layer is formed over the low-k dielectric layer by plasma enhanced chemical vapor deposition (PECVD), a resist layer is formed over the amorphous carbon doped layer , and the resist layer is patterned to define a first opening thereby forming a resist mask. The amorphous carbon doped layer is etched to define a second opening, thereby forming a hardmask, the resist mask is stripped, and the low-k dielectric layer not covered by the hardmask is etched to form a third opening as a trench or via.