Patents by Inventor Chun Feng

Chun Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230288709
    Abstract: A device for adjusting the degree of tightness is provided. The device is for a first strap element and a second strap element. The device includes an outer adjustment element, an inner adjustment element, and an intermediate adjustment element. The inner adjustment element is disposed inside the outer adjustment element. The intermediate adjustment element is disposed between the inner adjustment element and the outer adjustment element. The first strap element includes a first hollow region, and the second strap element includes a second hollow region. The inner adjustment element passes through the first hollow region and the second hollow region to adjust the degree of overlapping of the first hollow region and the second hollow region.
    Type: Application
    Filed: June 21, 2022
    Publication date: September 14, 2023
    Inventors: Chun-Feng YEH, Chun-Lung CHEN, Chun-Nan HUANG, Bing-Kai HUANG, Jia-Cheng CHANG
  • Publication number: 20230289588
    Abstract: A deep neural network (DNN) processing device with a decompressing module, comprises a storage module, for storing a plurality of binary codes, a coding tree, a zero-point value and a scale; a decompressing module, coupled to the storage module, for generating a quantized weight array according to the plurality of binary codes, the coding tree and the zero-point value wherein the quantized weight array is generated according to an aligned quantized weight array and the zero-point value; and a DNN processing module, coupled to the decompressing module, for processing an input signal according to the quantized weight array and the scale.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: ALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Feng Huang, Jung-Hsuan Liu, Chao-Wen Lin
  • Patent number: 11756221
    Abstract: Image processing performed on images captured with image capture devices may be used to improve upon some of the problems with images captured from devices, including images captured from devices with larger aperture lenses, and, in some particular examples, mobile devices with larger aperture lenses. Multiple images may be captured by the capture device and processing applied to generate a single image through fusing of the multiple images. One potential benefit obtained with fusion of multiple images is a single image with an effective depth of focus (DOF) larger than that available in a single image obtained from the capture device. The DOF of the fused image may be larger than a single image and/or may include multiple distinct in-focus focal distances, whereas a single image from a single capture device has only a single in-focus focal distance.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: September 12, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Wen-Chun Feng, Hsuan-Ming Liu, Yu-Ren Lai
  • Publication number: 20230261055
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 11727537
    Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced image effects, such as bokeh effect, applied in image processing. In a first aspect, a method of image processing includes determining a depth map corresponding to the first scene based on first image data and second image data captured at different aperture sizes; determining a focus map based on the depth map and a simulated aperture size different from the first aperture size and the second aperture size; and determining an output image frame based on the focus map, the first image data, and the second image data. Other aspects and features are also claimed and described.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: August 15, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Wen-Chun Feng, Hui Shan Kao, Kai Liu
  • Patent number: 11728219
    Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh, Chiao-Ting Tai
  • Publication number: 20230214557
    Abstract: A method for dynamically assessing slope safety includes the following steps: S1, carrying out geologic model generalization to the slope according to slope type, slope structure, stratum characteristics and a deformation failure mode to obtain a slope geologic model, creating a slope geometric model according to the slope geologic model, carrying out the subdivision of computational grid, and selecting a reasonable numerical simulation method, mechanical constitutive and initial boundary value conditions to form a computational model; and S2, adjusting stratum parameters, structural plane parameters and activating factor strength based on the computational model, carrying out a large amount of numerical simulation, summarizing results of the numerical simulation, normalizing input quantities and output quantities to establish machine learning samples.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 6, 2023
    Applicant: INSTITUTE OF MECHANICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Chun FENG, Xinguang ZHU, Pengda CHENG, Yu ZHOU, Lixiang WANG, Yongbo FAN, Li ZHANG
  • Publication number: 20230208084
    Abstract: A power plug device includes a first housing, a circuit board, a wire assembly and a second housing. The first housing includes an upper-housing body, a through hole and an inner cover. An accommodating portion is arranged in the upper-housing body, the through hole is formed on one side of the upper-housing body, the inner cover is installed in the accommodating portion, a receptive space is arranged in the inner cover, and the through hole interconnects with the receptive space. The wire assembly includes core wires, which passes through the through hole and the receptive space, so that the core wires are accommodated in the accommodating portion, and the receptive space is suitable for accommodating glue to secure the core wires and provides waterproof effect. In addition, dual-layered waterproof structure is used to make the first and second housing joining together having stronger waterproof effect.
    Type: Application
    Filed: January 25, 2022
    Publication date: June 29, 2023
    Inventor: Chun-Feng Chang
  • Publication number: 20230187447
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Yu-Chang LIN, Chun-Feng NIEH, Huicheng CHANG, Hou-Yu CHEN, Yong-Yan LU
  • Patent number: 11677012
    Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsan-Chun Wang, Chun-Feng Nieh, Chiao-Ting Tai
  • Publication number: 20230172191
    Abstract: A vitrification device for gametes or embryos, wherein, the vitrification straw comprises: a loading rod, wherein the loading rod is a metal rod; a loading strip, wherein, the loading strip is connected with one end of the loading rod. According to the present invention, the loading rod is arranged as metal rod, which avoids embrittlement fracture caused by sudden temperature change when the loading rod is taken out of liquid nitrogen, moreover, the ice crystals that form on gametes or embryos when the loading rod floats out of the surface of liquid nitrogen, affecting the safety of gametes or embryos, the metal material used by this invention can increase the weight of the loading rod, preventing it from floating up in the liquid nitrogen, hence improve safety of gametes or embryos.
    Type: Application
    Filed: November 4, 2022
    Publication date: June 8, 2023
    Inventors: Jinpeng Rao, Min Jin, Shen Tian, Chun Feng, Fan Jin, Ya Yu
  • Patent number: 11671715
    Abstract: A device for camera processing is configured to receive a preview image, and determine if the preview image is a high dynamic range (HDR) scene based on brightness values of pixels of the preview image. The device may further determine to use a single frame image capture technique based on a determination that the preview image is not an HDR scene, and determine to use one of a plurality of HDR image capture techniques based on a determination that the preview image is an HDR scene, and further based on motion detected in the preview image. The device may then generate an output image using one or more images captured using the single frame image capture technique or one of the plurality of HDR image capture techniques.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: June 6, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Tai-Hsin Liu, Wen-Chun Feng, Wei-Chih Liu, Jun-Zuo Liu
  • Patent number: 11670683
    Abstract: A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm?3 and about 1020 cm?3.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Publication number: 20230156301
    Abstract: Aspects of the present disclosure relate to systems and methods for image focusing for devices including multiple cameras. An example method includes estimating a focus distance associated with an image captured by a first camera, determining, based at least in part on the estimated focus distance, to switch from the first camera to a second camera, switching from the first camera to the second camera, completing a focusing operation using the second camera and presenting an updated image captured by the second camera.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 18, 2023
    Inventors: Wen-Chun FENG, Mian LI
  • Patent number: 11640986
    Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
  • Patent number: 11640255
    Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: May 2, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Ting-Hsuan Lo, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11593489
    Abstract: A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 28, 2023
    Assignee: MaxLinear, Inc.
    Inventors: Jiaxiang Shi, Chun Feng Hu, Yao Chye Lee, Qiming Wu
  • Patent number: 11594277
    Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 28, 2023
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11574907
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Publication number: 20230017498
    Abstract: A method of camera processing including receiving a first image, determining one or more first automatic white balance (AWB) parameters for the first image, determining one or more second AWB parameters for a region-of-interest (ROI) of the first image, applying the one or more first AWB parameters to one or more of the first image or a second image, and adjusting the ROI of one or more of the first image or the second image based on the one or more second AWB parameters.
    Type: Application
    Filed: January 18, 2022
    Publication date: January 19, 2023
    Inventors: Wen-Chun Feng, Wei-Chih Liu, Yi-Chun Hsu, Tai-Hsiang Jen