Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.

Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.

Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.

Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.

Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; a

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. The first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. The first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. The second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. The metal rail extends in an X-direction and adjacent to the gate structure in a Y-direction. The first source/drain contact and the second source/drain contact each has an L-shape in a Y-Z cross-sectional view. The first source/drain contact electrically connects the first source/drain feature to the metal rail. The second source/drain contact electrically connects the fourth source/drain feature to the metal rail.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.

Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.

Abstract: A method includes forming a channel region above a (110)-orientated substrate and having a length extending in a <100> direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.

Abstract: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

Abstract: The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.