Abstract: An exposure time determination method for image sensing operation includes: providing a first stage exposure condition which includes a first exposure time; sensing an image according to the first stage exposure condition to generate a first histogram which has a first histogram brightness maximum, a first histogram brightness minimum, and a first histogram width; increasing or decreasing the first exposure time to a second exposure time as a second stage exposure condition, and sensing the image according to the second stage exposure condition to generate a second histogram which has a second histogram brightness maximum, a second histogram brightness minimum, and a second histogram width; comparing the first histogram width with the second histogram width to generate a comparison result, and determining a third exposure time to be a third stage exposure condition according to the comparison result; and sensing the image according to the third stage exposure condition.

Abstract: A vapor reduction device for a semiconductor wafer has a plurality of heat plates which are spaced arranged longitudinally for receiving a plurality of wafers, the heat plates are integrated into a heating frame which is further placed into a casing. The movements of the heat plates within the casing causes that the wafers can be heated rapidly and uniformly so as to evaporated vapor effectively. The heat plates are separable from the heating frame and thus a number of the heat plates is selectable as desired. The heating temperature for the heat plates is controllable independently so that the temperatures of the wafers are controllable so that the temperature differences of the wafers are controllable to be uniformly distributed.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: An object labeling system includes a first object labeling module, a second object label model, a label integrating module and an inter-frame tracking module. The first object label module is configured to generate a first object labeling result according to a first 2D image, wherein the first 2D image is one of the frames of a 2D video. The second object labeling module is configured to generate a second 2D image according to a 3D information, and to generate a second object labeling result according to the 3D information and the second 2D image. The label integrating is configured to generate a third object labeling result according to the first object labeling result and the second object labeling result. The inter-frame tracking module is configured to perform an inter-frame object labeling process according to the third object labeling result to generate a fourth object labeling result.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.

Abstract: A novel distributed graph database is provided that is designed for efficient graph data storage and processing on modern computing architectures. In particular a single node graph database and a runtime & communication layer allows for composing a distributed graph database from multiple single node instances.

Abstract: Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.

Abstract: A display device including a panel having a gate driver is provided. The gate driver includes a multi-stage shift register. The N-th stage shift register includes a control module, a leakage compensation module, and an output module. The control module has a first terminal for receiving a first signal from the (N?M)-th stage shift register and a second terminal electrically connected to a node for transmitting a first signal to the node. The leakage compensation module has a third terminal electrically connected to the compensation voltage and a fourth terminal electrically connected to the node. The output module has a fifth terminal electrically connected to the node for receiving the first signal, and a sixth terminal for outputting a second signal of the N-th stage shift register for driving at least some parts of the pixel array. The compensation voltage charges the node during a touch sensing period.

Abstract: A lung sound monitoring device is provided. The lung sound monitoring device includes an acoustic sensor and a processor. The acoustic sensor is configured to capture the chest cavity sound of a subject at a first monitoring position on the subject and convert the chest cavity sound into a first chest cavity sound signal. The processor is configured to receive the first chest cavity sound signal and perform a filter process to obtain a first lung sound signal, and convert the first lung sound signal into a first lung sound spectrum using time-domain frequency-domain conversion. The processor acquires a first intensity index according to the first lung sound spectrum, and outputs a prompt signal according to the first intensity index to indicate whether the first monitoring position is a qualified monitoring position.

Abstract: A plasma etching reaction chamber includes a casing having a receiving chamber; a base liftably installed below the receiving chamber; a first electrode and a second electrode; and a radio frequency electrode rod. The second electrode has a plurality of water channels and a bottom of the second electrode is installed with two cooling water tubes which are communicated with the plurality of water channels; upper sides of the two cooling water tubes are hidden within the driving rod and lower sides thereof extend downwards to be out of the casing so that external cooling water can flow into the cooling water tubes and then to the water channels to achieve the object of cooling.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

Abstract: A socket connector includes an insulating housing, at least one docking element, a plurality of docking terminals, a fastening board and an outer cover assembly. A middle of the insulating housing has at least one holding groove. The at least one docking element is assembled in the at least one holding groove. The at least one docking element defines a plurality of docking grooves. The plurality of the docking terminals are fastened in the plurality of the docking grooves, separately. The fastening board has a first opening. The insulating housing is fastened to a rear surface of the fastening board. The outer cover assembly is assembled in the first opening. The outer cover assembly includes a frame and a waterproof element. The waterproof element has a sleeving ring, a covering portion, and a connecting element connected between the sleeving ring and the covering portion.

Abstract: A heat exchange system includes a cold source, a heat dissipation apparatus, a water storage tank, a heating portion, and a cooling portion. The heating portion is coupled between the cold source and the water storage tank. The cooling portion is coupled between the heat dissipation apparatus and the water storage tank. The cooling portion transmits heat of the heat dissipation apparatus to water of the water storage tank to cool the heating portion, and the heating portion transmits heat of the water of the water storage tank to the cold source to heat the cold source.

Abstract: An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes an anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL.

Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

Abstract: The mat of the present invention includes a main body integrally formed by a plastic material. The main body at least has a first surface and a second surface adjacent to the first face. The first face and the second face have different surface physical characteristics. The first surface and the second surface are shaped into a third surface and a fourth surface respectively. The third surface and the fourth surface have a substantially same surface physical characteristic. An angle between the third surface and the fourth surface outside the main body is a specific value.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.