Abstract: A container data center includes a container, two server cabinet groups, and a power supply equipment group. The container includes an interior. The two server cabinet groups are respectively arranged at two opposite ends of the interior of the container. The power supply equipment group is arranged in the container between the two server cabinet groups.

Abstract: An apparatus is provided for detecting transmittance of a trench. The trench is located on an infrared-transmittable material, which can be a wafer. The wafer is obtained after a ditching process. An image of the wafer is fetched. The contrast of the image is greatly enhanced. The contrast-enhanced image is used for automated analysis of the transmittance of the trench. Accuracy of detecting the transmittance is improved. Hence, the present invention uses a simple structure to detect transmittance defects of the trench for ensuring goodness of the wafer.

Abstract: A multi-band spectrum division device is provided, comprising: a first parabolic reflection mirror, planar multi-mirrors, an optical grating and a second parabolic mirror. The first parabolic mirror is configured to reduce the divergent angle of incident optical beam, and to generate a collimated optical beam. The planar multi-mirrors are configured to adjust the incident angles of collimated beam on the grating surface. The grating is configured to disperse the incident signals with multi-wavelengths. The second parabolic mirror is configured to focus the multi-wavelength signals on its focal plane. Besides, each of the planar multi-mirrors has different location and angle in this device.

Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.

Abstract: A network card with searching ability inquires connection information from all network cards at a network by using a broadcasting manner when it is connected to the same network, and build a connection list according to the received connection information. A user terminal can connect to a management page by one of the network cards on the network by a browser thereon, and check the connection list at the management page upon login successfully. User can obtain connection information of all network cards at the network through the connection list. Therefore, the user terminal can connect to a target network card according to the obtained connection information through a redirection manner. Else, it can also connect to the target network card via the logged network card through a relay manner.

Abstract: An apparatus is provided for detecting transmittance of a trench. The trench is located on an infrared-transmittable material, which can be a wafer. The wafer is obtained after a ditching process. An image of the wafer is fetched. The contrast of the image is greatly enhanced. The contrast-enhanced image is used for automated analysis of the transmittance of the trench. Accuracy of detecting the transmittance is improved. Hence, the present invention uses a simple structure to detect transmittance defects of the trench for ensuring goodness of the wafer.

Abstract: A light-emitting device comprises a carrier; and a first semiconductor element comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is to the carrier, the first semiconductor structure comprises a first MQW structure configured to emit a first light having a first dominant wavelength during normal operation, and the second semiconductor structure comprises a second MQW structure configured not to emit light during normal operation.

Abstract: A vibrating and massaging bed includes a supporting base member having one or more spring biasing members for supporting a follower, an actuating device disposed in the supporting base member and connected to the follower for vibrating the follower relative to the supporting base member, a sliding member slidably engaged in the follower and a table supported on the sliding member, and another actuating device coupled to the sliding member for moving the sliding member and the table relative to the follower. A further actuating device is engaged in the sliding member and includes an actuating rod extendible out of the sliding member for tilting the table relative to the sliding member and the follower.

Abstract: The invention provides a gate driving circuit for an in-cell touch panel to improve the issue wherein the undesired falling time of a pre-stage shift register and the undesired rising time of a next-stage shift register during a touch sensing period, in which the undesired falling time and the undesired rising time are caused by the output signal of the shift register cannot be correctly transmitted to the pre-stage shift register and the next-stage shift register during the touch sensing period.

Abstract: The present invention provides a measurement system of real-time spatially-resolved spectrum and time-resolved spectrum and a measurement module thereof. The measurement system includes an excitation light and a measurement module. The excitation light excites a fluorescent sample and the measurement module receives and analyzes fluorescence emitted by the fluorescent sample. The measurement module includes a single-photon linear scanner and a linear CCD spectrometer. The single-photon linear scanner selectively intercepts a light beam component of a multi-wavelength light beam that has a predetermined wavelength to generate a single-wavelength time-resolved signal, wherein the multi-wavelength light beam is generated by splitting the fluorescence. The linear CCD spectrometer receives the multi-wavelength light beam and generates a spatially-resolved full-spectrum fluorescence signal.

Abstract: A gate driving circuit includes a plurality of shift registers connected in series. The shift registers include a plurality of output shift registers and X groups of dummy shift registers. The output shift registers output the gate driving signal to a plurality of gate driving lines of the pixel matrix in sequence. At least one of the X groups of dummy shift registers has J dummy shift registers and is connected between two adjacent output shift registers in the output shift registers, wherein at least one driving signal generated by the group of dummy shift registers is partially overlapped with the gate driving signal generated by the two adjacent output shift registers in a frame, wherein the X groups of dummy shift registers are not connected to the gate driving lines, and X and J are integers greater than zero.

Abstract: A system for processing a semiconductor wafer includes a database configured to store data including relationships between device pattern characteristics, chemical mechanical polishing (CMP) conditions, and CMP performance, a data analyzer configured to predict performance of a CMP process to be performed on a wafer based on wafer design data and the relationships included in the database, and an output device configured to output the predicted performance of the CMP process.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.

Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.

Abstract: A scanning method of a display changes a driving order of a plurality of gate driver lines so as to reduce switching currents generated while a plurality of voltages on a plurality of source driver lines are changed. Thereby, the goal of saving power can be reached.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: The present disclosure provides an event reconstruction system including a communication unit, a key information integration device, a storage unit and a computation unit. The key information integration device receives key information from a plurality of image capturing device through the communication unit. The key information includes a first identification code and a second identification code retrieved from a first image capturing device and a second image capturing device respectively. The storage unit stores the key information. The computation unit extracts the key information and confirms the second image capturing device transmitting the second identification code according to the first identification code and the second identification code in the key information.