Patents by Inventor Chun Geik Tan
Chun Geik Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8442451Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.Type: GrantFiled: June 30, 2010Date of Patent: May 14, 2013Assignee: Marvell International Ltd.Inventors: Chun-Geik Tan, Randy Tsang, Wayne A. Loeb
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Publication number: 20130034190Abstract: Wireless receiver for receiving a plurality of co-existing wireless signals respectively from different positioning systems, includes an analog frontend and an analog-to-digital converting unit. The analog frontend is arranged to convert bands of the co-existing wireless signals into a plurality of corresponding intermediate bands by a local frequency and to provide an intermediate signal including the intermediate bands. The analog-to-digital converting unit is coupled to the analog frontend, and is arranged to convert the intermediate signal to a digital signal, wherein an operation band of the analog-to-digital converting unit covers the plurality of intermediate bands.Type: ApplicationFiled: December 2, 2011Publication date: February 7, 2013Applicant: MEDIATEK SINGAPORE PTE. LTD.Inventors: Chun-Geik Tan, Wei-Min Shu, Chi-Hsueh Wang
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Publication number: 20130029627Abstract: An amplifier receives an input signal with an input node, provides an output signal in response, and includes a main branch and an auxiliary branch. The auxiliary branch is coupled between the input node and a splitting node for input matching of the input node. The main branch, also coupled to the splitting node, has an output node of current mode, and is arranged to output the output signal at the output node. An associated receiver is also disclosed.Type: ApplicationFiled: November 4, 2011Publication date: January 31, 2013Applicant: MEDIATEK SINGAPORE PTE. LTD.Inventors: Fei Song, Chun-Geik Tan
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Patent number: 8319547Abstract: A system and method for voltage controlled oscillator (VCO) biasing in low voltage circuits including low resistance elements that are especially susceptible to noise. In one embodiment, a poly resistor and triode resistor is used to cancel or offset the effects that temperature variations have on the circuit. The triode resistor is powered by a voltage source that uses a pair of diodes coupled to a constant transconductance (gm) circuit to generate a reduced noise voltage that is independent of the power supply noise. The size of the triode resistor and poly resistors can be varied.Type: GrantFiled: January 27, 2010Date of Patent: November 27, 2012Assignee: Marvell International Ltd.Inventors: Chun-Geik Tan, Randy Tsang, Yonghua Song
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Publication number: 20120019305Abstract: A signal converting device includes: a reference signal-mixing circuit arranged to generate a reference mixing output signal according to an input signal, a reference gain, and a reference local oscillating signal; a plurality of auxiliary signal-mixing circuits, each arranged to generate an auxiliary mixing output signal according to the input signal, an auxiliary gain, and an auxiliary local oscillating signal; and a combining circuit arranged to combine the reference mixing output signal and a plurality of the auxiliary mixing output signals to generate an output signal, and at least one of the auxiliary signal-mixing circuits is configured by the corresponding auxiliary gain to compensate phase imbalances between the reference mixing output signal and each of the auxiliary mixing output signals to reduce a power of a harmonic component in the output signal.Type: ApplicationFiled: May 8, 2011Publication date: January 26, 2012Inventors: Huajiang Zhang, Chun Geik Tan
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SIGNAL GENERATOR AND SIGNAL STRENGTH DETECTING CIRCUIT HAVING THE SIGNAL GENERATOR INSTALLED THEREIN
Publication number: 20120019298Abstract: A signal generator includes: an adjusting circuit arranged to adjust a first amplitude of an oscillating signal to generate an adjusted oscillating signal; and a resistor ladder circuit arranged to receive the adjusted oscillating signal to generate a plurality of candidate output oscillating signals having a plurality of different amplitudes respectively and output an output oscillating signal selected from the candidate output oscillating signals.Type: ApplicationFiled: May 8, 2011Publication date: January 26, 2012Inventors: Dan Ping Li, Chun Geik Tan -
Patent number: 7852168Abstract: Energy-efficient timing circuits are described. Such circuits may include a biasing circuit configured to provide a control bias current to a voltage-controlled oscillator (VCO). The biasing circuit may repetitively switch between a normal-power operating mode and a reduced-power operating mode. During the normal-power operating mode, the biasing circuit may generate a control voltage representative of a desired control bias current for the VCO. By then storing the control voltage using a device, such as a capacitor, much of the biasing circuit may be turned off during the reduced-power operating mode.Type: GrantFiled: August 17, 2007Date of Patent: December 14, 2010Assignee: Marvell International Ltd.Inventors: Yonghua Song, Chun Geik Tan, Randy Tsang, Chunwei Chang
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Patent number: 7821318Abstract: A mixer includes first and second differential input pairs that include first and second transistors. First and second bias transistors receive a first signal of a differential input signal that is the one of a first phase and a second phase, and that respectively communicate with first terminals of the first and second transistors of the first differential input pair. Third and fourth bias transistors receive a second signal of the differential input signal, and that respectively communicate with first terminals of the first and second transistors of the second differential input pair. First and second capacitive elements have first and second ends that respectively communicate with the first terminals of the first and second transistors of the first and second differential input pairs. Four current sourcing elements respectively communicate with first terminals of the first, second, third, and fourth bias transistors.Type: GrantFiled: June 2, 2008Date of Patent: October 26, 2010Assignee: Marvell International Ltd.Inventors: Chun Geik Tan, Naratip Wongkomet
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Patent number: 7756486Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.Type: GrantFiled: October 5, 2006Date of Patent: July 13, 2010Assignee: Marvell International Ltd.Inventors: Chun-Geik Tan, Randy Tsang, Wayne A. Loeb
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Patent number: 7667533Abstract: A system and method for voltage controlled oscillator (VCO) biasing in low voltage circuits including low resistance elements that are especially susceptible to noise. In one embodiment, a poly resistor and triode resistor is used to cancel or offset the effects that temperature variations have on the circuit. The triode resistor is powered by a voltage source that uses a pair of diodes coupled to a constant transconductance (gm) circuit to generate a reduced noise voltage that is independent of the power supply noise. The size of the triode resistor and poly resistors can be varied.Type: GrantFiled: October 24, 2006Date of Patent: February 23, 2010Assignee: Marvell International Ltd.Inventors: Chun-Geik Tan, Randy Tsang, Yonghua Song
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Patent number: 7528667Abstract: A capacitor bank adapted to provide a variable capacitance to an electronic circuit is provided. The capacitor bank has at least a most significant bit and a least significant bit and includes a first capacitor cell having a first capacitance value and disposed between a first node and a second node, thereby forming the most significant bit. The capacitor bank also includes a second capacitor cell having a second capacitance value and disposed between the first node and the second node, thereby forming the least significant bit. The second capacitance value is less than the first capacitance value. Additionally, the second capacitor cell includes a first T-network capacitor unit in electrical communication with a source of a transistor and a second T-network capacitor unit in electrical communication with a drain of the transistor.Type: GrantFiled: July 19, 2006Date of Patent: May 5, 2009Assignee: Marvell International Ltd.Inventors: Chun Geik Tan, Randy Tsang, Yonghua Song
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Patent number: 7518417Abstract: A frequency divider comprises a first differential input pair, a second differential input pair, a first capacitive element having first and second ends, a second capacitive element having first and second ends, and four current sourcing elements. The first differential input pair includes first and second transistors that receive a differential local oscillator signal. The second differential input pair includes first and second transistors that receive the differential local oscillator signal. The first capacitive element communicates with first terminals of the transistors of the first differential input pair. The second capacitive element communicates with first terminals of the transistors of the second differential input pair. The four current sourcing elements respectively communicate with the first terminals of the transistors of the first and second differential input pairs.Type: GrantFiled: February 1, 2007Date of Patent: April 14, 2009Assignee: Marvell International Ltd.Inventors: Chun Geik Tan, Naratip Wongkomet
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Patent number: 7486154Abstract: An oscillating circuit having improved noise degeneration includes an oscillator and a noise degeneration circuit. The oscillator is adapted to provide a differential oscillating signal between first and second output terminals, and includes first and second transistors in communication with the first and second output terminals. The noise degeneration circuit includes cross-coupled capacitors and cross-coupled third and fourth transistors operated in a linear region. The noise degeneration circuit reduces the low frequency gm of the first and second transistors to lower the effect of flicker noise. At relatively high frequencies, the capacitors provide a virtual AC ground to the source terminals of the first and second transistors. The noise degeneration circuit receives a voltage signal from a biasing circuit adapted to track variations in electrical characteristics of the third and fourth transistors.Type: GrantFiled: October 30, 2006Date of Patent: February 3, 2009Assignee: Marvell International Ltd.Inventors: Chun Geik Tan, Randy Tsang
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Patent number: 7332971Abstract: A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.Type: GrantFiled: June 10, 2004Date of Patent: February 19, 2008Assignee: Agency for Science, Technology and ResearchInventors: Uday Dasgupta, Chun Geik Tan
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Patent number: 7092692Abstract: A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs?Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.Type: GrantFiled: March 31, 2003Date of Patent: August 15, 2006Assignees: Agency for Science, Technology and Research, Oki Techno Center (Singapore) Pte. LTDInventors: Chun Geik Tan, Masaaki Itoh
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Patent number: 6839399Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.Type: GrantFiled: March 31, 2003Date of Patent: January 4, 2005Assignee: Agency for Science, Technology and ResearchInventors: Chun Geik Tan, Uday Dasgupta
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Publication number: 20040192244Abstract: A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs−Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: Agency For Science, Technology And ResearchInventors: Chun Geik Tan, Masaaki Itoh
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Publication number: 20040190673Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: Agency For Science, Technology And ResearchInventors: Chun Geik Tan, Uday Dasgupta