Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.

Abstract: Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.

Abstract: A backlight module includes a film, a light guide plate disposed under the film, and a circuit board disposed under the light guide plate and provided with a light-emitting unit. The film includes a single-key transparent area, a light-shielding area disposed around the single-key transparent area, and a side transparent area disposed adjacent to or along an edge of the film. The light guide plate has a first microstructure group and a through hole correspondingly disposed under the single-key transparent area, a second microstructure group correspondingly disposed under the side transparent area, and a light-transmitting area partially correspondingly disposed under the light-shielding area. The light-emitting unit is accommodated in the through hole. A number of microstructures or a light-emitting area of the second microstructure group is greater than a number of microstructures or a light emitting area of the first microstructure group.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source/drain region and extending vertically along a sidewall of the silicide. A source/drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.

Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.

Abstract: A semiconductor device is provided, which includes a semiconductor stack and a first contact structure. The semiconductor stack includes an active layer and has a first surface and a second surface. The first contact structure is located on the first surface and includes a first semiconductor layer, a first metal element-containing structure and a first p-type or n-type layer. The first metal element-containing structure includes a first metal element. The first p-type or n-type layer physically contacts the first semiconductor layer and the first metal element-containing structure. The first p-type or n-type layer includes an oxygen element (O) and a second metal element and has a thickness less than or equal to 20 nm, and the first semiconductor layer includes a phosphide compound or an arsenide compound.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. A bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.

Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.

Abstract: An optical system applied to an optical biometer is disclosed. The optical system includes a light source, first and second switchable reflectors, and first and second fixed reflectors. The first switchable reflector is disposed corresponding to the light source. The second switchable reflector is disposed corresponding to an eye. In a first mode, the first and second switchable reflectors are switched to a first state, and the incident light emitted by the light source is reflected by the first fixed reflector along a first optical path and then emitted to a first position of the eye. In a second mode, the first and second switchable reflectors are switched to a second state, and the incident light is sequentially reflected by the first switchable reflector, the second fixed reflector and the second switchable reflector along a second optical path and then emitted to a second position of the eye.

Abstract: An integrated circuit includes a first region of the integrated circuit including a first set of pins extending in a first direction, being on a first level, and having a first width in a second direction different from the first direction. The first region has a first height in the second direction. An integrated circuit further includes a second region of the integrated circuit adjacent to the first region, the second region including a second set of pins extending in the first direction, being on a first level, being separated from the first set of pins in the second direction, and having a second width in the second direction, the first width being different from the second width. The second region has a second height in the second direction different from the first height, and the first level is a first metal layer of the integrated circuit.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: A magnetic component includes a core and at least one coil. The core includes at least one outer leg and an inner leg. The inner leg is separated from an upper inner surface of the core. The inner leg is at least partially divided into a plurality of separated portions along a length direction of the inner leg. The at least one coil is wound around the inner leg.

Abstract: A magnetic component includes a core, at least one coil, a first heat dissipating member and a second heat dissipating member. The core includes at least one outer leg and an inner leg. The at least one coil is wound around the inner leg. The first heat dissipating member is disposed on a first side and a top side of the core. The second heat dissipating member is disposed on a second side and the top side of the core. The first heat dissipating member and the second heat dissipating member have a first joint region, a second joint region and a third joint region on the top side. Projections of the first joint region and the second joint region do not overlap with the inner leg. A projection of at least one of the first heat dissipating member and the second heat dissipating member overlaps with the inner leg.

Abstract: An electronic device includes a temporary storage base, an adhesive layer, light-emitting elements, and a sealant. The adhesive layer is disposed on the temporary storage base. The light-emitting elements are disposed on the adhesive layer. The sealant is disposed on the temporary storage base and surrounds the adhesive layer. In addition, other electronic devices and a manufacturing method of the electronic device are also provided.

Abstract: The present invention provides a measuring method for prolonging a usage lifetime of a biosensor to measure a physiological signal representative of a physiological parameter associated with an analyte in a biofluid. The biosensor includes two working electrodes at least partially covered by a chemical reagent and two counter electrodes having silver and a silver halide, and each silver halide has an initial amount.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.