Patents by Inventor Chun-Hao Liao
Chun-Hao Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12387457Abstract: An image capturing device with a sensor, a memory, and a processor is provided. The sensor captures an image of at least one target. The memory stores a plurality of instructions. The processor obtains the plurality of instructions to perform the following steps: controlling the sensor to capture a reference image and a processed image; capturing a first bright region and a dark region from the reference image, and capturing a second bright region from the processed image; performing calculations on a first brightness value of the first bright region and a second brightness value of the second bright region respectively with at least two first brightness thresholds, to obtain a first low exposure compensation value and a second low exposure compensation value; and obtaining a high exposure compensation value according to comparisons between a third brightness value of the dark region and at least two second brightness thresholds.Type: GrantFiled: August 25, 2022Date of Patent: August 12, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Chun-Hao Liao, Hsiu-Ting Yang
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Publication number: 20240223746Abstract: A method and a device for detecting power stability of an image sensor are provided. The method includes: providing first power by a power supply circuit to the image sensor based on a first electronic configuration; during a period that the image sensor is driven by the first power, capturing at least one first test image by the image sensor; analyzing image content of the first test image to obtain first noise distribution information of the first test image; and generating a first evaluation information corresponding to the first electronic configuration according to the first noise distribution information.Type: ApplicationFiled: September 19, 2023Publication date: July 4, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Chen-Jeh Wu, Hsiu-Ting Yang, Chun-Hao Liao
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Patent number: 12020993Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.Type: GrantFiled: March 11, 2021Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hao Liao, Yu Chuan Liang, Chu Fu Chen
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Publication number: 20240087966Abstract: A driver structure for an organic light-emitting diode (OLED) device is provided. The driver structure includes a front-end-of-line (FEOL) layer; a back-end-of-line (BEOL) layer disposed on the FEOL layer; and a customer BEOL layer disposed on the BEOL layer. The BEOL layer includes a customer BEOL electrical checking structure. The customer BEOL electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. The customer BEOL layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. The first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.Type: ApplicationFiled: February 17, 2023Publication date: March 14, 2024Inventors: Chu Fu Chen, Chun Hao Liao
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Publication number: 20240055295Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: October 29, 2023Publication date: February 15, 2024Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Patent number: 11842920Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: GrantFiled: June 21, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
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Publication number: 20230252552Abstract: An e-gifting method is provided. The method is performed by a computer device including a processing unit, and includes: receiving, by the processing unit, gift filtering information and receiver information from a giver terminal device; generating, by the processing unit, a candidate gift list according to the gift filtering information and the receiver information, where the candidate gift list includes a plurality of candidate gift items; generating, by the processing unit, a gifting list from the candidate gift items according to giver selecting information from the giver terminal device, where the gifting list includes a plurality of gifting gift items; confirming, by the processing unit, a selected gift item from the gifting gift items according to receiver selecting information from a receiver terminal device; and transmitting, by the processing unit, payment information corresponding to the selected gift item to the giver terminal device.Type: ApplicationFiled: September 7, 2022Publication date: August 10, 2023Inventors: Kuo-Chung CHIU, Hsuan-Wu WEI, Yi-Hua HUANG, Chun-Hao LIAO
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Publication number: 20230085693Abstract: An image capturing device with a sensor, a memory, and a processor is provided. The sensor captures an image of at least one target. The memory stores a plurality of instructions. The processor obtains the plurality of instructions to perform the following steps: controlling the sensor to capture a reference image and a processed image; capturing a first bright region and a dark region from the reference image, and capturing a second bright region from the processed image; performing calculations on a first brightness value of the first bright region and a second brightness value of the second bright region respectively with at least two first brightness thresholds, to obtain a first low exposure compensation value and a second low exposure compensation value; and obtaining a high exposure compensation value according to comparisons between a third brightness value of the dark region and at least two second brightness thresholds.Type: ApplicationFiled: August 25, 2022Publication date: March 23, 2023Inventors: Chun-Hao LIAO, Hsiu-Ting YANG
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Publication number: 20220293477Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: CHUN HAO LIAO, YU CHUAN LIANG, CHU FU CHEN
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Publication number: 20210313218Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Patent number: 11107737Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.Type: GrantFiled: April 29, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
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Patent number: 11075107Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: GrantFiled: April 1, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
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Patent number: 11024552Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.Type: GrantFiled: January 10, 2020Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Mingo Liu, Chiou Jun Yean
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Publication number: 20200152526Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.Type: ApplicationFiled: January 10, 2020Publication date: May 14, 2020Inventors: Chun Hao LIAO, Chu Fu CHEN, Mingo LIU, Chiou Jun YEAN
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Publication number: 20200105582Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.Type: ApplicationFiled: April 1, 2019Publication date: April 2, 2020Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
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Patent number: 10535572Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.Type: GrantFiled: June 27, 2016Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hao Liao, Chu Fu Chen, Mingo Liu, Chiou Jun Yean
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Publication number: 20190252272Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
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Patent number: 10276457Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.Type: GrantFiled: March 29, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
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Publication number: 20180286765Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
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Publication number: 20170301659Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.Type: ApplicationFiled: June 27, 2016Publication date: October 19, 2017Inventors: Chun Hao LIAO, Chu Fu CHEN, Mingo LIU, Chiou Jun YEAN