Patents by Inventor Chun-Hao Liao

Chun-Hao Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12387457
    Abstract: An image capturing device with a sensor, a memory, and a processor is provided. The sensor captures an image of at least one target. The memory stores a plurality of instructions. The processor obtains the plurality of instructions to perform the following steps: controlling the sensor to capture a reference image and a processed image; capturing a first bright region and a dark region from the reference image, and capturing a second bright region from the processed image; performing calculations on a first brightness value of the first bright region and a second brightness value of the second bright region respectively with at least two first brightness thresholds, to obtain a first low exposure compensation value and a second low exposure compensation value; and obtaining a high exposure compensation value according to comparisons between a third brightness value of the dark region and at least two second brightness thresholds.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: August 12, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Hao Liao, Hsiu-Ting Yang
  • Publication number: 20240223746
    Abstract: A method and a device for detecting power stability of an image sensor are provided. The method includes: providing first power by a power supply circuit to the image sensor based on a first electronic configuration; during a period that the image sensor is driven by the first power, capturing at least one first test image by the image sensor; analyzing image content of the first test image to obtain first noise distribution information of the first test image; and generating a first evaluation information corresponding to the first electronic configuration according to the first noise distribution information.
    Type: Application
    Filed: September 19, 2023
    Publication date: July 4, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chen-Jeh Wu, Hsiu-Ting Yang, Chun-Hao Liao
  • Patent number: 12020993
    Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hao Liao, Yu Chuan Liang, Chu Fu Chen
  • Publication number: 20240087966
    Abstract: A driver structure for an organic light-emitting diode (OLED) device is provided. The driver structure includes a front-end-of-line (FEOL) layer; a back-end-of-line (BEOL) layer disposed on the FEOL layer; and a customer BEOL layer disposed on the BEOL layer. The BEOL layer includes a customer BEOL electrical checking structure. The customer BEOL electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. The customer BEOL layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. The first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 14, 2024
    Inventors: Chu Fu Chen, Chun Hao Liao
  • Publication number: 20240055295
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Application
    Filed: October 29, 2023
    Publication date: February 15, 2024
    Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
  • Patent number: 11842920
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
  • Publication number: 20230252552
    Abstract: An e-gifting method is provided. The method is performed by a computer device including a processing unit, and includes: receiving, by the processing unit, gift filtering information and receiver information from a giver terminal device; generating, by the processing unit, a candidate gift list according to the gift filtering information and the receiver information, where the candidate gift list includes a plurality of candidate gift items; generating, by the processing unit, a gifting list from the candidate gift items according to giver selecting information from the giver terminal device, where the gifting list includes a plurality of gifting gift items; confirming, by the processing unit, a selected gift item from the gifting gift items according to receiver selecting information from a receiver terminal device; and transmitting, by the processing unit, payment information corresponding to the selected gift item to the giver terminal device.
    Type: Application
    Filed: September 7, 2022
    Publication date: August 10, 2023
    Inventors: Kuo-Chung CHIU, Hsuan-Wu WEI, Yi-Hua HUANG, Chun-Hao LIAO
  • Publication number: 20230085693
    Abstract: An image capturing device with a sensor, a memory, and a processor is provided. The sensor captures an image of at least one target. The memory stores a plurality of instructions. The processor obtains the plurality of instructions to perform the following steps: controlling the sensor to capture a reference image and a processed image; capturing a first bright region and a dark region from the reference image, and capturing a second bright region from the processed image; performing calculations on a first brightness value of the first bright region and a second brightness value of the second bright region respectively with at least two first brightness thresholds, to obtain a first low exposure compensation value and a second low exposure compensation value; and obtaining a high exposure compensation value according to comparisons between a third brightness value of the dark region and at least two second brightness thresholds.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 23, 2023
    Inventors: Chun-Hao LIAO, Hsiu-Ting YANG
  • Publication number: 20220293477
    Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Inventors: CHUN HAO LIAO, YU CHUAN LIANG, CHU FU CHEN
  • Publication number: 20210313218
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
  • Patent number: 11107737
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 11075107
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Chun-Wei Hsu, Chia-Cheng Pao
  • Patent number: 11024552
    Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Mingo Liu, Chiou Jun Yean
  • Publication number: 20200152526
    Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Inventors: Chun Hao LIAO, Chu Fu CHEN, Mingo LIU, Chiou Jun YEAN
  • Publication number: 20200105582
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
  • Patent number: 10535572
    Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hao Liao, Chu Fu Chen, Mingo Liu, Chiou Jun Yean
  • Publication number: 20190252272
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 10276457
    Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Publication number: 20180286765
    Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Publication number: 20170301659
    Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 19, 2017
    Inventors: Chun Hao LIAO, Chu Fu CHEN, Mingo LIU, Chiou Jun YEAN