Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.

Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.

Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: A method for compensating the frequency dependent phase imbalance in a receiver is provided. The receiver downconverts an input signal to generate the signal r(t). The signal r(t) has an in-phase component rI(t) and a quadrature component rQ(t). A first test signal with a first carrier frequency is applied as the input signal of the receiver to obtain a first phase imbalance I. A second test signal with a second carrier frequency is applying as the input signal of the receiver to obtain a second phase imbalance. An IQ delay mismatch ?t of the receiver according to the difference of the second and the first phase imbalances and the difference of the second and the first carrier frequencies is obtained. The in-phase component rI(t) and the quadrature component rQ(t) of the signal r(t) corresponding to other input signal is compensated according to the obtained IQ delay mismatch ?t.

Abstract: A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.

Abstract: An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

Abstract: A communication unit includes: a quadrature transmitter having analog transmit filter(s) for filtering a first quadrature test signal. An analog feedback loopback path selectively first routes the filtered quadrature first test signal to a quadrature receiver. The quadrature receiver has: at least one analog receive filter for further filtering the filtered quadrature first test signal; and a quadrature receive baseband circuit arranged to receive and decode the further filtered quadrature first test signal.

Abstract: A communication unit includes: a quadrature transmitter having analog transmit filter(s) for filtering a first quadrature test signal. An analog feedback loopback path selectively first routes the filtered quadrature first test signal to a quadrature receiver. The quadrature receiver has: at least one analog receive filter for further filtering the filtered quadrature first test signal; and a quadrature receive baseband circuit arranged to receive and decode the further filtered quadrature first test signal.

Abstract: A method for compensating the frequency dependent phase imbalance in a transmitter is provided. The transmitter processes a baseband signal. The method includes the following steps: (a) compensating the baseband signal with a predetermined delay amounts; (b) inputting the compensated baseband signal to an upconversion circuit to generate a radio frequency (RF) signal; (c) inputting the RF signal to a delay information extractor to obtain a correlation value related to the information of the predetermined delay amount; (d) changing the predetermined delay amount and compensating the baseband signal again with the changed predetermined delay amount, and performing steps (b) and (c) again to update the correlation value; and (e) selecting a candidate delay amount from the predetermined delay amount according to the correlation value, and compensating the transmitter by using the candidate delay amount.

Abstract: A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

Abstract: A method for compensating the frequency dependent phase imbalance in a transmitter is provided. The transmitter processes a baseband signal. The method includes the following steps: (a) compensating the baseband signal with a predetermined delay amounts; (b) inputting the compensated baseband signal to an upconversion circuit to generate a radio frequency (RF) signal; (c) inputting the RF signal to a delay information extractor to obtain a correlation value related to the information of the predetermined delay amount; (d) changing the predetermined delay amount and compensating the baseband signal again with the changed predetermined delay amount, and performing steps (b) and (c) again to update the correlation value; and (e) selecting a candidate delay amount from the predetermined delay amount according to the correlation value, and compensating the transmitter by using the candidate delay amount.

Abstract: A method for compensating the frequency dependent phase imbalance in a receiver is provided. The receiver downconverts an input signal to generate the signal r(t). The signal r(t) has an in-phase component rI(t) and a quadrature component rQ(t). A first test signal with a first carrier frequency is applied as the input signal of the receiver to obtain a first phase imbalance I. A second test signal with a second carrier frequency is applying as the input signal of the receiver to obtain a second phase imbalance. An IQ delay mismatch ?t of the receiver according to the difference of the second and the first phase imbalances and the difference of the second and the first carrier frequencies is obtained. The in-phase component rI(t) and the quadrature component rQ(t) of the signal r(t) corresponding to other input signal is compensated according to the obtained IQ delay mismatch ?t.

Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Abstract: A device includes a first power supply line carrying a first positive power supply voltage, and a second power supply line carrying a second positive power supply voltage lower than the first positive power supply voltage. The device further includes a protection circuit having a MOS transistor. A diode is coupled to the MOS transistor. The source-to-drain path of the MOS transistor and the diode are serially coupled between the first and the second power supply lines. The diode is forward biased by the first and the second positive power supply voltages.

Abstract: An ejecting mechanism capable of preventing an accidental touch is disposed in a housing having a tray and used for ejecting the tray out of the housing. The ejecting mechanism includes a tray ejecting button and a front cover. The front cover is disposed at the housing and located at the ejecting direction of the tray. The front cover has a sliding key including a pressing body and a triggering body connected to one end of the pressing body. When the pressing body drives the triggering body to slide until the triggering body aligns to the tray ejecting button, the pressing body is capable of being forced to drive one end of the triggering body to trigger the tray ejecting button to eject the tray.