Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.

Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.

Abstract: A method for encrypting on-screen contents, an electronic apparatus using the method, and a recording medium using the method are provided. The method is adapted for the electronic apparatus having a screen. In the method, contents are displayed on the screen. A user's operation is then detected to generate a trigger signal. The displayed contents are encrypted according to the trigger signal.

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.

Abstract: An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding layer over the LD die and the adhesive layer. The method still further includes curing the molding layer and partially removing the molding layer to expose the laser emitting area. The method also includes depositing a ridge waveguide structure adjacent to the laser emitting area and depositing an upper cladding layer over the ridge waveguide structure.

Abstract: A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer.

Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.

Abstract: An approach is provided for forming a light coupling in a waveguide layer. The approach involves forming a waveguide layer overlaying an upper surface of a substrate. The approach also involves placing a chip package portion within the waveguide layer in a selected position. The approach further involves forming a molding compound layer overlaying the waveguide layer and the chip package portion. The approach additionally involves curing the molding compound layer to form a cured package. The approach also involves releasing the cured package from the substrate and inverting the cured package. The approach further involves forming a ridge waveguide structure in the waveguide layer by removing a portion of the lower surface of the cured package.

Abstract: An attachable monitoring device includes a battery unit, a wiring board unit and a physical condition sensor and an adhesive. The battery unit includes a top surface, a bottom surface and a plurality of side surfaces connecting the top surface and the bottom surface. The wiring board unit covers the top surface, the bottom surface and one of the side surfaces and electrically connected to the battery unit. The wiring board unit includes a printed antenna printed on a first outer surface of the wiring board unit. The physical condition sensor is disposed on a second outer surface of the wiring board unit opposite to the first outer surface. The physical condition sensor includes a sensing region for contacting a user to detecting a physical-condition signal of the user. The adhesive is disposed on the wiring board unit for being attached to the user.

Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Abstract: A method and an apparatus for correcting wireless signal quality are provided. The apparatus includes an abnormality detector and a quality adjuster. The abnormality detector collects multiple measurement values reported by a user equipment (UE), calculates a variation degree value according to the measurement values, and compares the variation degree value with a predetermined threshold value. The measurement values are generated by the UE when the UE measures the wireless signal quality of an evolved node B. The measurement values include a first reference signal receiving quality (RSRQ) of the evolved node B. When the variation degree value is larger than the predetermined threshold value, the quality adjuster corrects the first RSRQ based on the measurement values to generate a second RSRQ of the evolved node B.

Abstract: A manufacture includes a package structure, a first substrate, and a conductive member of a same material. The package structure includes a chip comprising a conductive pad, a conductive structure over the chip, and a passivation layer over the conductive structure. The passivation layer has an opening defined therein, and the opening exposes a portion of a planar portion of the conductive structure. The first substrate includes a first surface defining a first reference plane and a second surface defining a second reference plane. The conductive member extends across the first reference plane and the second reference plane and into the opening. The conductive member is electrically coupled to the exposed portion of the planar portion.

Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.

Abstract: A vacuum carrier module includes a substrate having at least one hole and an edge region. There is at least one support on a top surface of the substrate. Further, a gel film is adhered to the edge region of the substrate. The at least one hole fluidly connects a reservoir located above the top surface of the substrate. A method of using a vacuum carrier module includes planarizing a gel film by passing an alignment material through a hole in a substrate to contact a first surface of the gel film, positioning at least one chip on a second surface of the gel film opposite the first surface. The method further includes encasing the at least one chip in a molding material and applying a vacuum to the first surface of the gel film.

Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Abstract: An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding layer over the LD die and the adhesive layer. The method still further includes curing the molding layer and partially removing the molding layer to expose the laser emitting area. The method also includes depositing a ridge waveguide structure adjacent to the laser emitting area and depositing an upper cladding layer over the ridge waveguide structure.

Abstract: An approach is provided for forming a light coupling in a waveguide layer. The approach involves forming a waveguide layer overlaying an upper surface of a substrate. The approach also involves placing a chip package portion within the waveguide layer in a selected position. The approach further involves forming a molding compound layer overlaying the waveguide layer and the chip package portion. The approach additionally involves curing the molding compound layer to form a cured package. The approach also involves releasing the cured package from the substrate and inverting the cured package. The approach further involves forming a ridge waveguide structure in the waveguide layer by removing a portion of the lower surface of the cured package.

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.