Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.

Abstract: A learning method for improving performance of a knowledge graph embedding model is provided. The method includes: performing learning of a first knowledge graph embedding model based on input knowledge data; extracting all embedding vectors from the learned first knowledge graph embedding model, and extracting prior knowledge based on the extracted embedding vectors; and performing learning of a second knowledge graph embedding model through at least one of initialization of the embedding vectors and transform of the input knowledge data based on the extracted prior knowledge.

Abstract: A self-evolving agent-based simulation system generates model evolution strategy for applying a difference between real-data and a simulation resulting value to a simulation model, and reconstructing components included in the simulation module using the model evolution strategy to evolve the simulation model when the difference between the real-data and the simulation resulting value of the agent-based simulation model does not satisfy a value in a predetermined error range.

Abstract: A system and method for calibrating a simulation model based on a framework. The system includes a calibration parameter value generating processor configured to generate a value of a first calibration parameter for calibrating microdata and a value of a second calibration parameter for calibrating a simulating processor; an initial data generating processor configured to determine a missing value of the microdata based on the value of the first calibration parameter to generate initial data; and the simulating processor configured to simulate based on the initial data and the value of the second calibration parameter.

Abstract: A self-evolving agent-based simulation system generates model evolution strategy for applying a difference between real-data and a simulation resulting value to a simulation model, and reconstructing components included in the simulation module using the model evolution strategy to evolve the simulation model when the difference between the real-data and the simulation resulting value of the agent-based simulation model does not satisfy a value in a predetermined error range.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer.

Abstract: A clustering apparatus of probabilistic graphs, includes a center selection unit configured to select one or more centers among the probabilistic graphs. The clustering apparatus further includes a center determination unit configured to calculate a minimum bound and a maximum bound of a distance with respect to each of the centers, for each of the probabilistic graphs, and determine a center, among the centers, to which the probabilistic graphs are to be allocated based on the minimum and maximum bounds. The clustering apparatus further includes a clustering unit configured to allocate the probabilistic graphs to the center to generate one or more clusters.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer.

Abstract: A clustering apparatus of probabilistic graphs, includes a center selection unit configured to select one or more centers among the probabilistic graphs. The clustering apparatus further includes a center determination unit configured to calculate a minimum bound and a maximum bound of a distance with respect to each of the centers, for each of the probabilistic graphs, and determine a center, among the centers, to which the probabilistic graphs are to be allocated based on the minimum and maximum bounds. The clustering apparatus further includes a clustering unit configured to allocate the probabilistic graphs to the center to generate one or more clusters.

Abstract: An apparatus and method for stably filtering duplicate data in various resource-restricted environments such as a mobile device and medical equipment are provided. The apparatus includes a cell array unit configured to comprise one or more cells; a duplication check unit configured to check whether input data is duplicate and set a value of a cell that matches the input data; and a duplication probability calculation unit configured to, in response to the input data being determined as duplicate data by the duplication check unit, calculate a probability of duplication of the input data using the set value of the cell. Data which may be duplicate data among a large amount of input data is not arbitrarily deleted, but is provided to an application along with a probability of duplication of the data. Accordingly, a false positive error that occurs in Bloom filter is prevented, and thereby system stability can be improved.

Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

Abstract: A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.

Abstract: In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the conductive pattern and surrounding sidewalls of each pillar pattern, and the gate electrode is formed by etching the conductive pattern using the spacer as an etch barrier.

Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.

Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.

Abstract: Provided are a method which stores data using a path encoding scheme and a region numbering scheme for supply chain management using RFID, a method which processes queries about data stored by the data storage method, and a data management system which manages data for the management of the supply chain using RFID by the data storage method and the query processing method. A massive amount of RFID data generated in supply chain management using the RFID can effectively be stored, and information of the movement path of any product can be obtained from the stored data easily and quickly.

Abstract: In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.