Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.

Abstract: An earphone includes a body with a surrounding side, a rotatable loop and an ear hook. The rotatable loop is pivotally connected with the body on two opposite ends of the surrounding side. The body and the rotatable loop can rotate with respect to a first axis and with respect to each other. The ear hook is pivotally mounted on one side of the rotatable loop near where the rotatable loop is connected with the body, and the ear hook can rotate with respect to a second axis, which is different from the first axis.

Abstract: According to an exemplary embodiment of the present disclosure, the ear-loop earphone comprises a main body, an ear-loop base and an ear-loop. The main body has a surrounding side, a front side, and a back side, wherein the front side is opposing to the back side, the front side has a plurality of sounding apertures for outputting an audio, and the surrounding side surrounds and connects to the front side and the back side. The ear-loop base is fixed on the surrounding side of the main body in a rotatable manner, and rotates with respect to a first axis. The ear-loop is fixed on the ear-loop base in a rotatable manner, and rotates with respect to a second axis different from the first axis.

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract: A touch panel display and method for manufacturing the same are disclosed. The touch panel display includes a first substrate, a second substrate, a touch-sensing member, and a liquid crystal layer. The first substrate has a first surface and a second surface thereon. The second substrate has an element array and is disposed on the second surface of the first substrate. The touch-sensing member locates on the first surface of the first substrate. Furthermore, the touch-sensing member includes a conductive layer, a patterned electrode layer, and a protective layer. The patterned electrode layer is correspondingly located on the periphery of the first substrate. The protective layer covers the conductive layer, and the patterned electrode layer. The conductive layer locates between the protective layer and the first substrate. In addition, the liquid crystal layer is disposed between the first and the second substrate.

Abstract: An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors.

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract: A liquid crystal display device includes a plurality of pixel driving circuits and a pixel array. Each pixel driving circuit of the plurality of pixel driving circuits includes four thin film transistors and has four output terminals, where each thin film transistor is used for driving an output terminal of the four output terminals, and the four output terminals are coupled to two gate lines and two sharing lines respectively for outputting two main output signals and two sharing output signals. The phases and timings of the two main output signals and the two sharing output signals are all the same. A pixel of the pixel array is charged/discharged to a specific voltage level according to a main output signal of the two main output signals, a sharing output signal, and a signal of a data line.

Abstract: An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors.

Abstract: An exemplary layout structure of a shift register circuit includes a first shift register and a second shift register arranged adjacent to the first shift register. The first shift register and the second shift register each receive a first signal and a second signal phase-inverted with respect to the first signal. Moreover, the first shift register and the second shift register share a common signal routing trace for receiving the first signal. The common signal routing trace is arranged extending into between the first shift register and the second shift register.

Abstract: A display device and method for manufacturing the same are disclosed. The display device includes a first substrate, a second substrate, a touch-sensing element, and a liquid crystal. The first substrate has a first surface and a second surface thereon. The second substrate has a pixel array and is disposed on the second surface of the first substrate. The touch-sensing element locates on the first surface of the first substrate. Furthermore, the touch-sensing element includes a conductive layer, a patterned electrode, and a passivation layer. The patterned electrode is correspondingly located on the periphery of the first substrate, and electrically connected to the conductive layer. The passivation layer covers the conductive layer and the patterned electrode. In addition, the liquid crystal is disposed between the first substrate and the second substrate.

Abstract: A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

Abstract: An ear hooked earphone is provided for selectively being worn on a left or right ear of a user. The earphone includes a body and an ear hook. The body includes a first coupled portion formed on a surface thereof. The ear hook includes a hook section and a fastened section. The hook section is used for hooking around the ear of the user. The fastened section is connected with the hook section, and a separation is formed between ends of the hook section and the fastened section. The fastened section has a second coupled portion, and one of two sides of the second coupled portion is selectively coupled with the first coupled section. Thereby, the position of the separation relative to the body is able to be changed, that is, the ear hooked earphone is able to hang on the left or right ear of the user freely.

Abstract: An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A liquid crystal display having touch input sensing includes a display panel and sensing units integrated in the display panel. The display panel has scan lines for delivering scan signals and readout lines for delivering readout signals. The sensing unit resets a sensing voltage according to a low-level voltage of the scan signal. Further, the sensing unit pulls up the sensing voltage according to a high-level voltage of the scan signal and an increase of the sensing voltage is under the control of a touch event. The readout signal is generated by the sensing unit based on the sensing voltage and the high-level voltage of the scan signal.

Abstract: The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.

Abstract: An active device array substrate includes a substrate, first scan lines, second scan lines, data lines, and pixels. The first and the second scan lines are alternately arranged along a first direction. The data lines are arranged in parallel along a second direction. The pixels are arranged to form first pixel rows and second pixel rows alternately arranged in the first direction. The first pixel row includes first and second pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The second pixel row includes third and fourth pixels electrically connected to the first scan lines, the second scan lines, and the data line, respectively. The pixels between two adjacent data lines are arranged in two columns. Among the pixels in the same column, the pixels in odd rows and in even rows are electrically connected to different data lines, respectively.