Patents by Inventor Chun-Hsiung Lin
Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9184289Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: GrantFiled: November 8, 2013Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
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Patent number: 9166035Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: GrantFiled: September 12, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Ta Lin, Mao-Lin Huang, Li-Ting Wang, Chien-Hsun Wang, Meng-Ku Chen, Chun-Hsiung Lin, Pang-Yen Tsai, Hui-Cheng Chang
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Patent number: 9147766Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: GrantFiled: November 14, 2013Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
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Publication number: 20150263094Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CARLOS H. DIAZ, CHUN-HSIUNG LIN, HUI-CHENG CHANG, SYUN-MING JANG, CHIEN-HSUN WANG, MAO-LIN HUANG
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Publication number: 20150255306Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
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Publication number: 20150228721Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.Type: ApplicationFiled: February 13, 2014Publication date: August 13, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: CHUN-HSIUNG LIN, CARLOS H. DIAZ, HUI-CHENG CHANG, SYUN-MING JANG, MAO-LIN HUANG, CHIEN-HSUN WANG
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Patent number: 9064959Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.Type: GrantFiled: May 15, 2013Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Kuo-Yin Lin, Wan-Chun Pan, Ming-Liang Yen, Huicheng Chang
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Patent number: 9048301Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: GrantFiled: October 16, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
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Publication number: 20150129938Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
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Publication number: 20150129981Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, CHUN-HSIUNG LIN, MAO-LIN HUANG
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Publication number: 20150108550Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN
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Publication number: 20150102287Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
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Publication number: 20150069467Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: HUNG-TA LIN, MAO-LIN HUANG, LI-TING WANG, CHIEN-HSUN WANG, MENG-KU CHEN, CHUN-HSIUNG LIN, PANG-YEN TSAI, HUI-CHENG CHANG
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Publication number: 20150044842Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Hong-Mao Lee, Huicheng Chang
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Publication number: 20140264362Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.Type: ApplicationFiled: May 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Kuo-Yin Lin, Wan-Chun Pan, Ming-Liang Yen, Huicheng Chang
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Publication number: 20080157958Abstract: An anti-theft device with a trigger applied in a portable electronic device is provided, which has a trigger electrically connected with a trigger unit selectively. When the trigger is separated from the trigger unit, a sensing element begins to carry out the sensing operation, and the portable electronic device is put into a power saving mode. When the sensing element senses that the electronic device has been moved, it transmits a signal to a processor. Meanwhile, the portable electronic device and an alarm unit of the trigger will be enabled simultaneously, making a sound to warn the user.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: INVENTEC CORPORATIONInventors: Chia-Yu Lin, Chun-Hsiung Lin
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Patent number: 7321771Abstract: A control method, capable of reducing the call dropped rate of a mobile station in a wireless communication system, includes monitoring receiving power levels of a plurality of neighbor cells of the wireless communication system according to an information of a serving cell of the wireless communication system; and if the Base Station Identification Codes (BSICs) of the six neighbor cells corresponding to the six strongest receiving power levels are known, and if the BSIC of at least one neighbor cell corresponding to at least one receiving power level other than the six strongest ones is unknown, performing frequency correction and synchronization of the mobile station with respect to the at least one neighbor cell's Broadcast Control Channel (BCCH) to decode the at least one neighbor cell's BSIC.Type: GrantFiled: November 29, 2004Date of Patent: January 22, 2008Assignee: Mediatek IncorporationInventors: Chun-Hsiung Lin, Sung-Yao Lin
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Patent number: 7321765Abstract: A timing method used by a mobile station in a wireless communication system. The timing method contains generating at least a buffering area in the mobile station; receiving a first action executed by a lower layer of the mobile station; after the mobile station receives the first action, updating a value stored in the buffering area; and if the value stored in the buffering area reaches a predetermined value, the mobile station performs a second action.Type: GrantFiled: November 25, 2004Date of Patent: January 22, 2008Assignee: MediaTek IncorporationInventors: Chun-Hsiung Lin, Sung-Yao Lin
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Patent number: 7312936Abstract: A digital image-capturing device includes an outer lens barrel, an image sensor disposed in the outer lens barrel, an inner lens barrel mounted in the outer lens barrel, and a lens module mounted in the inner lens barrel. The outer lens barrel has a barrel coupling segment formed with an internal screw thread, and a barrel guiding segment. The inner lens barrel has a barrel engaging segment formed with an external screw thread to engage threadedly the internal screw thread of the barrel coupling segment, and a barrel sliding segment in sliding and rotatable contact with the barrel guiding segment. When the inner lens barrel is inserted into the outer lens barrel, the barrel guiding segment can guide the barrel sliding segment to prevent the inner lens barrel from wobbling and to maintain optical axis alignment, thereby ensuring image-capturing quality of the device.Type: GrantFiled: November 14, 2005Date of Patent: December 25, 2007Assignee: Asia Optical Co., Inc.Inventors: Jung-Chun Yen, Chun-Hsiung Lin
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Publication number: 20060171047Abstract: A digital image-capturing device includes an outer lens barrel, an image sensor disposed in the outer lens barrel, an inner lens barrel mounted in the outer lens barrel, and a lens module mounted in the inner lens barrel. The outer lens barrel has a barrel coupling segment formed with an internal screw thread, and a barrel guiding segment. The inner lens barrel has a barrel engaging segment formed with an external screw thread to engage threadedly the internal screw thread of the barrel coupling segment, and a barrel sliding segment in sliding and rotatable contact with the barrel guiding segment. When the inner lens barrel is inserted into the outer lens barrel, the barrel guiding segment can guide the barrel sliding segment to prevent the inner lens barrel from wobbling and to maintain optical axis alignment, thereby ensuring image-capturing quality of the device.Type: ApplicationFiled: November 14, 2005Publication date: August 3, 2006Inventors: Jung-Chun Yen, Chun-Hsiung Lin