Patents by Inventor Chun-Hsiung Lin

Chun-Hsiung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160141423
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Application
    Filed: October 1, 2015
    Publication date: May 19, 2016
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20160126143
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 5, 2016
    Inventors: HUAN-CHIEH SU, JUI-CHIEN HUANG, CHUN-AN LIN, CHIEN-HSUN WANG, CHUN-HSIUNG LIN
  • Patent number: 9312186
    Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Chieh Su, Jui-Chien Huang, Chun-An Lin, Chien-Hsun Wang, Chun-Hsiung Lin
  • Publication number: 20160079358
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Inventors: Gerben DOORNBOS, Chun-Hsiung LIN, Chien-Hsun WANG, Carlos H. DIAZ
  • Publication number: 20160071966
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Application
    Filed: November 2, 2015
    Publication date: March 10, 2016
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
  • Publication number: 20160064493
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: CHUN-HSIUNG LIN, CARLOS H. DIAZ, HUI-CHENG CHANG, SYUN-MING JANG, MAO-LIN HUANG, CHIEN-HSUN WANG
  • Patent number: 9276084
    Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
  • Patent number: 9263295
    Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
  • Publication number: 20160043173
    Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 11, 2016
    Inventors: Yung-Sung YEN, Huan-Just LIN, Chun-Hsiung LIN, Chi-Cheng HUNG
  • Publication number: 20160013054
    Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Inventors: CHIEN-HSUN WANG, CHUN-HSIUNG LIN, MAO-LIN HUANG
  • Patent number: 9214513
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Hsiung Lin, Carlos H. Diaz, Hui-Cheng Chang, Syun-Ming Jang, Mao-Lin Huang, Chien-Hsun Wang
  • Patent number: 9184289
    Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
  • Patent number: 9166035
    Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ta Lin, Mao-Lin Huang, Li-Ting Wang, Chien-Hsun Wang, Meng-Ku Chen, Chun-Hsiung Lin, Pang-Yen Tsai, Hui-Cheng Chang
  • Patent number: 9147766
    Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
  • Publication number: 20150263094
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CARLOS H. DIAZ, CHUN-HSIUNG LIN, HUI-CHENG CHANG, SYUN-MING JANG, CHIEN-HSUN WANG, MAO-LIN HUANG
  • Publication number: 20150255306
    Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
    Type: Application
    Filed: May 26, 2015
    Publication date: September 10, 2015
    Inventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
  • Publication number: 20150228721
    Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 13, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: CHUN-HSIUNG LIN, CARLOS H. DIAZ, HUI-CHENG CHANG, SYUN-MING JANG, MAO-LIN HUANG, CHIEN-HSUN WANG
  • Patent number: 9064959
    Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Kuo-Yin Lin, Wan-Chun Pan, Ming-Liang Yen, Huicheng Chang
  • Patent number: 9048301
    Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
  • Publication number: 20150129981
    Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHIEN-HSUN WANG, CHUN-HSIUNG LIN, MAO-LIN HUANG