Patents by Inventor Chun-Huang Yu
Chun-Huang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12181518Abstract: The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.Type: GrantFiled: October 25, 2021Date of Patent: December 31, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chun-Huang Yu
-
Patent number: 11751334Abstract: The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.Type: GrantFiled: October 22, 2021Date of Patent: September 5, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chun-Huang Yu
-
Patent number: 11699686Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.Type: GrantFiled: March 3, 2022Date of Patent: July 11, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wu-Der Yang, Chun-Huang Yu
-
Publication number: 20230207512Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Inventors: Wu-Der YANG, Chun-Huang YU
-
Publication number: 20230126272Abstract: The present application discloses a semiconductor device with an interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Inventor: CHUN-HUANG YU
-
Publication number: 20230130078Abstract: The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.Type: ApplicationFiled: October 22, 2021Publication date: April 27, 2023Inventor: CHUN-HUANG YU
-
Patent number: 11469216Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.Type: GrantFiled: March 27, 2020Date of Patent: October 11, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wu-Der Yang, Chun-Huang Yu
-
Publication number: 20220189927Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Inventors: WU-DER YANG, CHUN-HUANG YU
-
Patent number: 11227814Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.Type: GrantFiled: March 16, 2020Date of Patent: January 18, 2022Assignee: Nanya Technology CorporationInventors: Wu-Der Yang, Chun-Huang Yu
-
Publication number: 20210305210Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: WU-DER YANG, CHUN-HUANG YU
-
Publication number: 20210287967Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.Type: ApplicationFiled: March 16, 2020Publication date: September 16, 2021Inventors: Wu-Der YANG, Chun-Huang YU
-
Publication number: 20210118838Abstract: A chip-package device includes a substrate, a first chip, a first conductive layer, first wirings, and second wirings. The substrate includes a first top surface and first connection pads disposed on the first top surface. The first chip is disposed on the first top surface, and the first chip includes a second top surface and second connection pads disposed on the second top surface. The first conductive layer is disposed on the second top surface. The first wirings connect the first connection pads and the first conductive layer, and the second wirings connect the second connection pads and another side of the first conductive layer. Each of the first wirings and each of the second wirings respectively connect opposite sides of the first conductive layer.Type: ApplicationFiled: October 16, 2019Publication date: April 22, 2021Inventors: Wu-Der YANG, Chun-Huang YU
-
Patent number: 9372512Abstract: A portable electronic device includes a cover, a main body, a first bracket, a second bracket and a rotary shaft. The main body includes a top surface, a bottom surface opposite to the top surface, and a guiding groove disposed on the top surface. One end of the first bracket pivots to the cover, and the other of the first bracket is slidable in the guiding groove. One end of the second bracket pivots to the cover. The rotary shaft pivots to the other of the second bracket and the main body to allow the second bracket to rotate about an axis of rotation relative to the main body. An orthographic projection of the guiding groove on the bottom surface of the main body and an orthographic projection of the rotary shaft on the bottom surface of the main body are overlapped with each other.Type: GrantFiled: April 15, 2014Date of Patent: June 21, 2016Assignee: COMPAL ELECTRONICS, INC.Inventors: Yao-Tsung Yeh, Kun-Hsin Liu, Shih-Chin Chou, Chun-Huang Yu, Hong-Tien Wang
-
Patent number: 9285838Abstract: An electronic device including a first body, a second body, a linking member, a plurality of keys, and an actuating module is provided. The first body has a display surface and the second body is adapted to be connected to the first body. The linking member is disposed within the second body. The keys are movably connected to the second body. The actuating module is disposed within the second body and located between the linking member and the keys. The linking member moves via a relative movement between the first body and the second body, so that the actuating module pushes the keys to move from the inside of the second body to the outside of the second body.Type: GrantFiled: December 10, 2013Date of Patent: March 15, 2016Assignee: COMPAL ELECTRONICS, INC.Inventors: Yao-Tsung Yeh, Kun-Hsin Liu, Wei-Hao Lan, Yen-Hsiao Yeh, Hong-Tien Wang, Shi-Kuan Chen, Chun-Huang Yu, Shih-Chin Chou
-
Patent number: 9137913Abstract: A portable electronic device adapted to be detachably connected to a cradle having a containing cavity is provided, wherein an inner wall of the containing cavity has a recess. The portable electronic device includes a body and a locking-and-releasing mechanism disposed in the body and including a driving unit and a latch. The driving unit is disposed in the body. The latch is connected to the driving unit and suitable for being driven by the driving unit to protrude out of the body or hide in the body. When the portable electronic device is disposed in the containing cavity, the driving unit drives the latch to protrude out of the body and be engaged with the recess. When the portable electronic device is going to be detached from the containing cavity, the driving unit drives the latch to be disengaged from the recess and move back in the body.Type: GrantFiled: March 15, 2013Date of Patent: September 15, 2015Assignee: COMPAL ELECTRONICS, INC.Inventors: Wei-Chih Hsu, Shi-Kuan Chen, Hong-Tien Wang, Yung-Hsiang Chen, Shih-Chin Gong, Yung-Ming Tien, Chun-Huang Yu, Chao-Tung Hsu, Jui-Che Hsu, Chih-Yin Lai, Chia-Sheng Liu
-
Patent number: 9104374Abstract: An electronic device including a first body, an input module and a functional element is provided. The input module is movably disposed on the first body and adapted to be moved between a first position and a second position. The functional element is disposed on the input module. When the input module is located at the first position, the functional element is concealed in the first body. When the input module is located at the second position, the functional element is exposed outside the first body.Type: GrantFiled: December 20, 2012Date of Patent: August 11, 2015Assignee: COMPAL ELECTRONICS, INC.Inventors: Hui-Jou Tsai, Yung-Hsiang Chen, Wen-Yi Chiu, Kuan-Yu Chou, Chuan-Hao Wen, Chun-Huang Yu, Chao-Tung Hsu, Chih-Yin Lai, Chia-Sheng Liu, Hsiang-Ling Liu
-
Publication number: 20150185786Abstract: A portable electronic device includes a cover, a main body, a first bracket, a second bracket and a rotary shaft. The main body includes a top surface, a bottom surface opposite to the top surface, and a guiding groove disposed on the top surface. One end of the first bracket pivots to the cover, and the other of the first bracket is slidable in the guiding groove. One end of the second bracket pivots to the cover. The rotary shaft pivots to the other of the second bracket and the main body to allow the second bracket to rotate about an axis of rotation relative to the main body. An orthographic projection of the guiding groove on the bottom surface of the main body and an orthographic projection of the rotary shaft on the bottom surface of the main body are overlapped with each other.Type: ApplicationFiled: April 15, 2014Publication date: July 2, 2015Applicant: COMPAL ELECTRONICS, INC.Inventors: Yao-Tsung YEH, Kun-Hsin LIU, Shih-Chin CHOU, Chun-Huang YU, Hong-Tien WANG
-
Patent number: 9072174Abstract: An electronic device includes a first body and a second body. The first body includes a first main body and a first magnetic element fixed in the first main body. The second body includes a second main body, a supporting unit, a second magnetic element, and a third magnetic element. The second main body is adapted to hold the first body. The supporting unit is pivoted to the second main body. The second magnetic element is fixed in the second main body. The third magnetic element is slidably configured in the second main body to restrict a rotation of the supporting unit relative to the second main body. When the first body leans against the second main body, the third magnetic element is subject to a magnetic attraction force from the first magnetic element and escapes from the supporting unit, so that the supporting unit supports the first body.Type: GrantFiled: October 8, 2013Date of Patent: June 30, 2015Assignee: COMPAL ELECTRONICS, INC.Inventors: Pei-Jen Lin, Wei-Chih Hsu, Sheng-Wei Wu, Chang-Hua Wei, Hui-Jou Tsai, Yao-Tsung Yeh, Kun-Hsin Liu, Wei-Hao Lan, Chun-Huang Yu, Pei-Yi Chu, Hong-Tien Wang, Shi-Kuan Chen
-
Patent number: 9035195Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.Type: GrantFiled: November 12, 2012Date of Patent: May 19, 2015Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Hsin-Mao Huang, Chun-Huang Yu
-
Patent number: 8982566Abstract: A memory module pair includes first and second memory modules. Each of the first and second memory modules includes a circuit board having opposite first and second side edges and a front edge, along which a plurality of pins are arranged. Each circuit board of the first and second memory modules has a key notch formed closer to the first side edge than to the second side edge. The circuit board of the first memory module has a corner notch that is formed on the front edge and the first side edge, while the circuit board of the second memory module has a corner notch that is formed on the front edge and the second side edge.Type: GrantFiled: May 16, 2012Date of Patent: March 17, 2015Assignee: Nanya Technology CorporationInventors: Hsin Mao Huang, Chun Huang Yu, Chih Yen Ho