Abstract: A touch panel and a manufacturing method thereof are provided. The touch panel includes a substrate, peripheral leads, a touch-sensing electrode, and first covers. The peripheral leads are disposed on the substrate. Each peripheral lead has a sidewall and an upper surface. The first covers cover the upper surfaces of the peripheral leads. The touch-sensing electrode includes a plurality of modified metal nanowires. The modified metal nanowires have first surfaces in direct contact with each other at an intersection. The modified metal nanowires have second surfaces with a covering structure, and the second surfaces are at non-intersections.

Abstract: A touch panel includes a substrate, a catalytic layer, peripheral traces, marks, first cover layers and second cover layers. The catalytic layer is formed on the peripheral area of the substrate, and the peripheral traces are formed on the catalytic layer. Each peripheral trace has a side wall and a top surface. The marks are formed on the catalytic layer, and each mark has a side wall and a top surface. The first cover layers cover the top surfaces of the peripheral traces, and the second cover layers cover the top surfaces of the marks. Each of the first cover layers and the second cover layers includes metal nanowires. The manufacturing method of the touch panel and a roll sheet of touch sensors are also disclosed.

Abstract: A touch panel and a manufacturing method thereof are provided. The touch panel includes a substrate, peripheral leads, a touch sensing electrode, and first intermediate layers. The peripheral leads are disposed in a peripheral area of the substrate. The first intermediate layers are disposed between the peripheral leads and the substrate. The touch sensing electrode includes a plurality of modified metal nanowires. The modified metal nanowires have first surfaces in direct contact with each other at an intersection. The modified metal nanowires have second surfaces with covering structures, and the second surfaces are at a non-intersection.

Abstract: A touch panel and a manufacturing method thereof are provided. The touch panel includes a substrate, peripheral leads, a touch-sensing electrode, and first covers. The peripheral leads are disposed on the substrate. Each peripheral lead has a sidewall and an upper surface. The first covers cover the upper surfaces of the peripheral leads. The touch-sensing electrode includes a plurality of modified metal nanowires. The modified metal nanowires have first surfaces in direct contact with each other at an intersection. The modified metal nanowires have second surfaces with a covering structure, and the second surfaces are at non-intersections.

Abstract: A conductive structure having a self-assembled protective layer and a self-assembled coating composition are provided. The self-assembled coating composition includes a resin, a solvent, and a self-assembled additive. The self-assembled additive includes alkylamine, fluoroalkylamine, fluoroaniline, or a derivative thereof. The self-assembled additive has a concentration in a range of from about 0.01 mg/L to about 100 mg/L in the self-assembled coating composition. The conductive structure includes a substrate, a conductive layer, and the self-assembled protective layer. The conductive layer is disposed over the substrate. The self-assembled protective layer covers the conductive layer and has a resin, a solvent, and the above-mentioned self-assembled additive.

Abstract: A method of manufacturing a touch panel including providing a substrate having a display area and a peripheral area is provided. A metal layer and a metal nanowire layer are disposed, wherein a first portion of the metal nanowire layer is disposed in the display area, and a second portion of the metal nanowire layer and the metal layer are disposed in the peripheral area. A patterned layer with a pattern is disposed. A patterning step is performed according to the patterned layer, wherein the patterning step includes forming the metal layer into multiple peripheral wires and simultaneously forming the second portion of the metal nanowire layer into multiple etching layers by using an etching solution configured to etch the metal layer and the metal nanowire layer. A touch panel is further provided.

Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.

Abstract: A touch panel includes a substrate, a catalytic layer, peripheral traces, marks, first cover layers and second cover layers. The catalytic layer is formed on the peripheral area of the substrate, and the peripheral traces are formed on the catalytic layer. Each peripheral trace has a side wall and a top surface. The marks are formed on the catalytic layer, and each mark has a side wall and a top surface. The first cover layers cover the top surfaces of the peripheral traces, and the second cover layers cover the top surfaces of the marks. Each of the first cover layers and the second cover layers includes metal nanowires. The manufacturing method of the touch panel and a roll sheet of touch sensors are also disclosed.

Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.

Abstract: A pixel structure is formed in a pixel area and coupled to a scan line and a data line. The pixel structure includes a first transistor, a second transistor and a pixel electrode. The first transistor is formed in the pixel area and coupled to the scan line and the data line. The second transistor is formed in the pixel area and coupled to the first transistor. The pixel electrode is formed in the pixel area and coupled to the second transistor. The pixel electrode includes a main portion and a first branch portion. The first branch portion is disposed between the first transistor and the second transistor. An electrophoretic display including the pixel structure is also disclosed herein.

Abstract: A pixel structure is formed in a pixel area and coupled to a scan line and a data line. The pixel structure includes a first transistor, a second transistor and a pixel electrode. The first transistor is formed in the pixel area and coupled to the scan line and the data line. The second transistor is formed in the pixel area and coupled to the first transistor. The pixel electrode is formed in the pixel area and coupled to the second transistor. The pixel electrode includes a main portion and a first branch portion. The first branch portion is disposed between the first transistor and the second transistor. An electrophoretic display including the pixel structure is also disclosed herein.

Abstract: An electro-phoretic display film includes a conductive layer, a dielectric layer disposed on the conductive layer, a plurality of electro-phoretic display media, and a sealing material. The dielectric layer has a plurality of micro-cups arranged in an array and a trench surrounding the micro-cups. The electro-phoretic display media are exclusively disposed within the micro-cups, and the sealing material is exclusively disposed within the trench.

Abstract: An electro-phoretic display film includes a conductive layer, a dielectric layer disposed on the conductive layer, a plurality of electro-phoretic display media, and a sealing material. The dielectric layer has a plurality of micro-cups arranged in an array and a trench surrounding the micro-cups. The electro-phoretic display media are exclusively disposed within the micro-cups, and the sealing material is exclusively disposed within the trench.

Abstract: An arranging-line mechanism comprises a cam, an axle connecting to the cam, a sliding element and a transmitting mechanism to drive the cam and the axle. The cam comprises an inclined surface and the sliding element to slide thereon. When the axle revolves, the transmitting mechanism drives the cam to revolve. A power line is wound regularly via the sliding element to slide on the inclined surface.

Abstract: An all-in-one adapter container. The all-in-one adapter container comprises a space, a cover covering the space, at least one power line, a printed circuit board (PCB) and at least one line-arranging mechanism. The line-arranging mechanism provides arrangement for the power line. The printed circuit board is electrically connected to the power line.

Abstract: A sphygmomanometer capable of adjusting a viewing angle of a display screen includes a housing, and the housing includes a lower casing and an upper casing. The lower casing includes a pivotal axle and a position limit mechanism. The upper casing has a containing space for containing a rotating body, and a display screen installed on a side of the rotating body, and a shaft protruded from another side of the rotating body which faces the lower casing. The shaft is sheathed onto the pivotal axle for the use of the sphygmomanometer. When the sphygmomanometer is worn onto a user's wrist or arm, the pivotal axle and the shaft are operated to turn the display screen on the rotating body to an appropriate position, so as to facilitate the user or medical professionals to view the reading of the measurement on the display screen.

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.