Abstract: An apparatus and a method are disclosed for performing a light-absorption measurement of a specified amount of sample. A method for performing a light-absorption measurement of a specified amount of sample includes placing the sample on the surface of an apparatus including the surface and a light reflector, the light reflector being mechanically coupled with the surface and separated from the surface by a separation distance, changing the separation distance, while the light reflector remains mechanically coupled with the surface, to a first separation distance, and performing a first light-absorption measurement of the sample via the apparatus, while the separation distance is equal to the first separation distance, and while the sample is subject to pressure force.

Abstract: The present invention relates to method for producing hypo-metallated redox-active metallothionein (MT) proteins, pharmaceutical compositions containing the proteins, and uses the pharmaceutical compositions for treatment of conditions originating from elevated intracellular oxidative stress and/or dis-balanced intracellular redox-potential and/or redox-potential-dependent imbalance of metal ions.

Abstract: A liquid display panel driving method to drive a plurality of pixels of a liquid display panel in a frame period comprising a plurality of data input intervals is provided. Each pixel comprises first and second capacitors coupled to a first and second common electrode respectively. The liquid display panel driving method comprises the steps of: keeping the second common electrode at the same voltage level; modifying the voltage of the first common electrode of each pixel along a row of scan line to perform a first pre-charge before the data input interval; turning on the pixels to make each pixel receive the data voltage from the data lines during the data input interval; and turning off the pixels and modifying the voltage of the first common electrode to further set the voltage of each of the pixels to a target level after the data input interval.

Abstract: The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor.

Abstract: An LCD device having dual source drivers and related driving method are disclosed for performing data signal driving operation by making use of a data writing synchronous control mechanism. The operation of the data writing synchronous control mechanism includes furnishing all image data signals to both the first and second source drivers, latching odd and even image data signals by the first and second source drivers respectively, performing a signal processing process on the odd image data signals for generating a first set of analog data signals by the first source driver, performing a signal processing process on the even image data signals for generating a second set of analog data signals by the second source driver, writing the first set of analog data signals into a plurality of first pixel units, and writing the second set of analog data signals into a plurality of second pixel units.

Abstract: A display includes a source driver, a demultiplexer, a first data line, a second data line, a first pixel and a second pixel. The demultiplexer includes a first pixel signal transmission unit and a second pixel signal transmission unit. The first pixel signal transmission unit includes a first sub-pixel signal transmission unit, a second sub-pixel signal transmission unit and a third sub-pixel signal transmission unit. The first sub-pixel signal transmission unit and the second sub-pixel signal transmission unit share a drain. A second pixel signal transmission unit next to the first pixel signal transmission unit includes a fourth sub-pixel signal transmission unit, a fifth sub-pixel signal transmission unit and a sixth sub-pixel signal transmission unit. The fourth sub-pixel signal transmission unit and the fifth sub-pixel signal transmission unit share another drain.

Abstract: A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.

Abstract: A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal.

Abstract: An antitussive composition is provided. A pharmaceutical composition for relieving, preventing and/or treating a cough includes a sufficient amount of the Morus australis Poir extract as an active component. The effective Morus australis Poir extract is prepared by extracting the root-bark of the Morus australis Poir with water, ethanol, acetone, ethyl acetate, or a combination thereof. The crude extract can be further fractioned by ultrafiltration or reverse phase column.

Abstract: A novel method and system for conducting wide-field multi-photon microscopy through plane-projection are provided. It has been discovered that the limitations of conventional temporal-focusing techniques, such as single excitation wavelength and low acquisition rates can be resolved utilizing a novel optical set-up in which an optical diffuser is used as the scatterer. The use of such an optical arrangement enables temporal focusing regardless of the central wavelength of laser pukes. In addition, the optical sectioning possible using the disclosed microscopy is comparable to confocal microscopy, and can be robustly achieved by both moderate and high NA objectives at 100-fs puke width. Moreover, the multi-photon excitation efficiency of the disclosed system can be enhanced by lowering the repetition rate of the ultrafast laser light source at constant pulse width and average power.

Abstract: A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.

Abstract: An arrangement method, applied to a plurality of gate driver modules coupled in series and arranged on two sides of a panel, includes steps of: placing a first gate driver module on a first side of the panel; placing a gate driver set on a second side of the panel; and placing a fourth gate driver module on the first side of the panel. The gate driver set includes a second gate driver module and a third gate driver module serially connected. The output terminal of the first gate driver module is electrically coupled to the second gate driver module and the output terminal of the third gate driver module is electrically coupled to the fourth gate driver module. A gate driver circuit and an arrangement method applied to a plurality of shift register sets coupled in series and arranged on two sides of a panel are also disclosed.

Abstract: The present invention relates to a memory circuit integrated in each pixel of a display device includes a switching circuit and a memory unit. The switching circuit includes a first transistor having a gate configured to receive a switching control signal, a source and a drain electrically coupled to a liquid crystal capacitor of the pixel, and a second transistor having a gate configured to receive a switching control signal, a source electrically coupled to a storage capacitor of the pixel, and a drain electrically coupled to the liquid crystal capacitor. The memory unit is electrically coupled between the source of first transistor and the storage capacitor.

Abstract: A data processing device applying for a storage device includes: a first interface circuit coupled to the storage device; a processing circuit coupled to the first interface circuit for reading a control code from a divided storage area in the storage device, and executing the control code to generate a storage capacity of the storage device; and a second interface circuit coupled to the processing circuit for feeding the storage capacity back to an operating system such that the operating system regards the storage capacity as a usable capacity of the storage device.

Abstract: A controlling circuit applicable in a physical storage device includes: a dividing circuit coupled to the physical storage device for dividing a storage capacity of the physical storage device into a plurality of divided storage areas, wherein a divided storage capacity of each divided storage area is not larger than the capacity corresponding to the largest address generated by an operating system; and a feedback circuit coupled to the dividing circuit for feeding back the plurality of divided storage areas to the operating system such that the operating system regards the plurality of divided storage areas as a plurality of independent physical storage devices.

Abstract: The present invention relates to a radiation curable and developable polyurethane which is characterized by having a carboxy group in its main chain and a acryloyl group in its side chain and comprising the following repeat units (I), (II), and (II) in a random arrangement: wherein R1, R2, R3, R4, and T are defined in the specification. The polyurethane has a weight molecular weight measured by GPC in a range of from 3,000 to 400,000; an acid value in a range of from 5 to 120 mgKOH/g. The present invention also relates to a radiation curable and developable composition containing the polyurethane.

Abstract: A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal.

Abstract: A timer controller and method of generating timing signals uses a synchronization signal and a clock signal to generate a timing signal by counting the clock signal only after the synchronization signal has changed states. In a display requiring a dot or line counter having n digits to meet the requirement of display resolution, it is possible to use a counter with k digits to generate a start signal, with 0?k<n. In particular, a start signal can be generated even without a counter.

Abstract: A data backup apparatus includes a host interface, a first storage medium interface, a second storage medium interface and a controller. The host interface is utilized to be electrically connected with a host, the first storage medium interface is utilized to be electrically connected with a first storage medium, and the second storage medium interface is utilized to be electrically connected with a second storage medium. The controller is coupled to the host interface, the first storage medium interface and the second storage medium interface, and is utilized for copying data from the first storage medium to the second storage medium without passing through the host interface.

Abstract: A method for configuring a network-attached storage (NAS) includes: coupling the network-attached storage to a user-end personal computer (PC) via an external bus which supports a plug & play function; and utilizing the user-end PC to configure a network interface of the NAS via the external bus. A network-attached storage (NAS) includes a network interface, a bus interface, and processor. The network interface is for connecting with a network. The bus interface is for connecting with an external bus which supports a plug & play function and for receiving network interface setting parameters outputted by a user-end PC via the external bus. The processor is coupled between the network interface and the bus interface, and implemented for configuring the network interface according to the network interface setting parameters received by the bus interface.