Abstract: A layout structure of an electronic element including an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and includes a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and includes a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract: A method of the measuring a critical dimension of a spacer is provided. The measurement is performed by using several test structures of measuring doping region resistance. Each of the test structure has different space disposed between a first gate line and a second gate line. By measuring a doping region resistance of each test structure, a plot of reciprocal of resistance versus space can be accomplished. Then, making regression of the plot, a correlation can be formed. Finally, a critical dimension of a spacer can be get by extrapolating the correlation back to 0 unit of reciprocal of resistance.

Abstract: A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage.

Abstract: A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution.

Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

Abstract: An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution.