Patents by Inventor Chun-Liang Hou

Chun-Liang Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134978
    Abstract: A high-electron mobility transistor includes a substrate; a buffer layer on the substrate; a AlGaN layer on the buffer layer; a passivation layer on the AlGaN layer; a source region and a drain region on the AlGaN layer; a source layer and a drain layer on the AlGaN layer within the source region and the drain region, respectively; a gate on the AlGaN layer between the source region and a drain region; and a field plate on the gate and the passivation layer. The field plate includes an extension portion that laterally extends to an area between the gate and the drain region. The extension portion has a wave-shaped bottom surface.
    Type: Application
    Filed: December 1, 2019
    Publication date: May 6, 2021
    Inventors: Chih-Tung Yeh, Shin-Chuan Huang, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20210111267
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 15, 2021
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 10971610
    Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao
  • Publication number: 20210098601
    Abstract: According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 1, 2021
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou, Chih-Tung Yeh
  • Publication number: 20210066484
    Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.
    Type: Application
    Filed: October 8, 2019
    Publication date: March 4, 2021
    Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20210036138
    Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: February 4, 2021
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao
  • Publication number: 20210013334
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.
    Type: Application
    Filed: August 7, 2019
    Publication date: January 14, 2021
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 10861970
    Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao, Ming-Chang Lu
  • Patent number: 10776402
    Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Chin Wang, Ya-Ching Cheng, Chien-Hung Chen, Chun-Liang Hou, Da-Ching Liao
  • Patent number: 10762618
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Hsu-Tang Liu, Yi-Jung Chang, Chun-Liang Hou
  • Publication number: 20200265573
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Pin-Yen TSAI, Hsu-Tang LIU, Yi-Jung CHANG, Chun-Liang HOU
  • Patent number: 10482153
    Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Ching Liao, Li-Chin Wang, Ya-Ching Cheng, Chien-Hung Chen, Chun-Liang Hou
  • Publication number: 20190266214
    Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 29, 2019
    Inventors: Da-Ching LIAO, Li-Chin Wang, Ya-Ching Cheng, Chien-Hung Chen, Chun-Liang Hou
  • Publication number: 20190087481
    Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.
    Type: Application
    Filed: November 22, 2017
    Publication date: March 21, 2019
    Inventors: Li-Chin Wang, Ya-Ching Cheng, Chien-Hung Chen, Chun-Liang Hou, Da-Ching Liao
  • Publication number: 20180314773
    Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Ya-Ching Cheng, Chun-Liang Hou, Chien-Hung Chen, Wen-Jung Liao, Min-Chin Hsieh, Da-Ching Liao, Li-Chin Wang
  • Patent number: 9964587
    Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Kuo Wang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20170328949
    Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Chien-Kuo Wang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20160334456
    Abstract: The fail bit count data, shmoo data, static noise margins and write margins corresponding to a wafer are measured. Using the above mentioned measurements, variables used to generate the curve are calculated. The variables used to generate the curve include the standard deviation of the fail bit count data, the static noise margins and the write margins. The curve is used to determine optimal operating condition of a fabrication process.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 17, 2016
    Inventors: Ya-Ching Cheng, Chun-Liang Hou, Hsiao-Kwang Yang, Chien-Jung Su, Guan-Lin Chen
  • Publication number: 20160019330
    Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: Chun-Ming Chang, Wen-Jung Liao, Chen-Wei Lee, Chun-Liang Hou
  • Patent number: 9235677
    Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: January 12, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Ming Chang, Wen-Jung Liao, Chen-Wei Lee, Chun-Liang Hou