Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

Abstract: According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.

Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.

Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.

Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.

Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

Abstract: The fail bit count data, shmoo data, static noise margins and write margins corresponding to a wafer are measured. Using the above mentioned measurements, variables used to generate the curve are calculated. The variables used to generate the curve include the standard deviation of the fail bit count data, the static noise margins and the write margins. The curve is used to determine optimal operating condition of a fabrication process.

Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract: A test key structure includes a plurality of transistors formed on a scribe line of a wafer and arranged in a 2*N array having 2 columns and N rows. The transistors arranged in the 2*N array respectively includes a gate, a source, a drain, and a body. All of the sources of the transistors arranged in the 2*N array are electrically connected to each other.

Abstract: A design layout generating method is provided. A design layout including a first pattern and a second pattern is provided to a computer system, wherein the first pattern and the second pattern meet a design rule of an integrated circuit, respectively. The first pattern and the second pattern are combined into a third pattern. Next, the third pattern is checked if it meets a definition of a weak pattern, wherein the weak pattern is a pattern that meets the design rule but still forms defects. Then, the third pattern is modified and a new design layout is generated.