Abstract: A method of extending a lifetime of a memory cell is provided. The method includes detecting, by a memory controller, whether a memory cell has failed or not; repairing, by the memory controller, the memory cell by applying a first pulse having a first amplitude to the memory cell, in response to determining that the memory cell has failed; and writing, by the memory controller, input data to the memory cell by applying a second pulse having a second amplitude less than the first amplitude, in response to repairing the memory cell. In one expect, the detecting includes writing, by the memory controller, additional input data to the memory cell; reading, by the memory controller, data stored by the memory cell; comparing, by the memory controller, the data stored by the memory cell with the additional input data; and determining whether the memory cell has failed according to the comparison.

Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.

Abstract: Disclosed is a method for processing a carbon fiber bundle, which can adjust bundling property, winding property and wear resistance of sizing fibers. The method includes following steps: (i) coating a sizing agent on at least one carbon fiber bundle, in which the sizing agent includes a thermoplastic resin; (ii) drying the carbon fiber bundle by hot air; and (iii) heating the carbon fiber bundle by an infrared light, in which a heating temperature of the heating is equal to or higher than a melting point of the thermoplastic resin.

Abstract: An automatic leveling device of a 3D printer, and a 3D printer is provided. The automatic leveling device includes a photoelectric switch, an electromagnetic assembly and a probe assembly. The photoelectric switch is arranged in a housing and defines a photosensitive groove. The electromagnetic assembly is arranged in the housing and defines a sliding hole. The probe assembly is slidably engaged in the sliding hole, and an end of the probe assembly is engaged in the photosensitive groove. The electromagnetic assembly is capable of driving the probe assembly to make the end of the probe assembly move out of the photosensitive groove. The automatic leveling device has the advantages of simple structure, low manufacturing difficulty, low production cost, simple and stable leveling mode, high detection repetition accuracy and no complex circuit and software cooperation.

Abstract: A key module includes a base plate, a circuit layer and a lifting mechanism. The circuit layer is disposed on the base plate. The lifting mechanism is pivotally connected with the base plate relative to the circuit layer, and the lifting mechanism has an abutment element. The abutment element could interfere with the circuit layer to reduce the noise generated by the key module during operation.

Abstract: A insertion module includes a main body, an auxiliary insertion seat, an insertion needle assembly and a sensor assembly. The main body has a plurality of slide grooves. The auxiliary insertion seat has a base portion, and a plurality of wing portions. The insertion needle assembly is fixed through the interference between the wing portions and wall surfaces of the slide grooves, such that the insertion needle is prevented from being oblique to an insertion direction before the insertion needle is inserted into a host.

Abstract: An electronic device including an active region and a peripheral region, and includes a substrate including a first edge and a second edge; a first electrode layer disposed on the substrate; a first conductive glue disposed on the substrate and in the peripheral region; a second conductive glue disposed on the substrate and in the peripheral region; an insulating glue overlapped with the first conductive glue and the second conductive glue; and a first metal element fixed on the first electrode layer through the first conductive glue and the insulating glue; wherein in a top view, the insulating glue is disposed in the peripheral region and extends along an extension direction parallel to the first edge, and along the extension direction, a first distance between the first conductive glue and the second edge is greater than a second distance between the second conductive glue and the second edge.

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.

Abstract: A copolyester is formed by copolymerizing a depolymerized polyester and succinic acid. The depolymerized polyester includes depolymerized polyethylene terephthalate (PET), and the depolymerized PET is formed by depolymerizing PET with ethylene glycol. The repeating unit of PET and the succinic acid have a molar ratio of 40:60 to 50:50. The repeating unit of PET and the ethylene glycol have a molar ratio of 100:100 to 100:500. The copolyester has a storage modulus of 1*104 Pa to 1*106 Pa at 80° C. The copolyester can be used in a hot melt adhesive.

Abstract: A deposition method, comprising the steps of exposing a carrier to moisture, so that a hydroxy group can be distributed on the surface of the carrier, and adding a liquid precursor to the hydroxy group to perform an alcohol condensation reaction to form a target atom layer or a target atom compound layer of the deposition carrier; the process provided by the present invention allows one or more liquid precursors to be freely selected for uniform deposition on the carrier. Compared to the current low-yield dry atomic deposition technology, it has no limitation on the volume of the reaction chamber, no complicated and diverse process, and can be designed as a continuous process to achieve wider industrial availability.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.

Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

Abstract: A touch system is provided. The touch system includes a touch tool and a touch panel. The touch tool provides a downlink signal. The touch panel obtains a first sensing area sensed with the touch tool, and obtains a second sensing area other than the first sensing area according to the downlink signal. The touch panel provides a first uplink signal to the first sensing area, and provides a second uplink signal to the second sensing area. The first uplink signal is different from the second uplink signal. The touch tool generates a calculated uplink signal according to the first uplink signal and the second uplink signal, and provides the downlink signal according to the calculated uplink signal.

Abstract: An immersion cooling system includes a tank, an isolation plate and a condenser. The tank includes a base plate and a sidewall connected with the base plate. The sidewall defines with the base plate a space configured to accommodate a cooling liquid. The isolation plate connects with the sidewall or the base plate and divides the space into a first subsidiary space and a second subsidiary space. The first subsidiary space is configured to accommodate electronic equipment which is immersed in the cooling liquid. The isolation plate and the base plate are separated from each other. The sidewall surrounds the condenser. A vertical projection of the condenser towards the base plate at least partially overlaps with the second subsidiary space. The electronic equipment evaporates a portion of the cooling liquid to form a vapor. The condenser is configured to condense the vapor into a liquid form.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.