Patents by Inventor Chun Lin

Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071854
    Abstract: Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi LIN, Kuang-Chun LEE, Chien-Chen LI, Chien-Li KUO, Kuo-Chio LIU
  • Publication number: 20240067746
    Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
  • Publication number: 20240066816
    Abstract: A dyeing method for functional contact lenses includes the following steps: providing a dry lens body, including hydrogel with 0-90% water content, silicone hydrogel with 0-90% water content, or a combination thereof; preparing an amphoteric polymethyl ether prepolymer, combining the amphoteric polymethyl ether prepolymer with a hydrophilic monomer to form a masking ring material, and attaching the masking ring material to an inner surface of the dry lens body to form a masking ring layer; dropping a colorant onto the inner surface, making the masking ring layer surround the colorant, irradiating the colorant with an ultraviolet light and then heating and fixing the colorant to form a dyed layer on the inner surface; and placing the dry lens body in water to hydrate and removing the masking ring layer to obtain a wet lens body.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Ching LIN, Ching-Fang LEE, Chi-Ching CHEN, Hsiao-Chun LIN
  • Publication number: 20240069729
    Abstract: An example method for optimizing data deletion in a storage system comprises: detecting a command to delete data from a storage volume using a file system, the data stored on one or more blocks within a storage device associated with the storage volume; monitoring a load metric associated with the storage volume, the load metric indicative of a dynamically changing operational load of the storage volume; and initiating, based on the detecting the command and on the monitored load metric, a discard request for the storage device, the discard request commanding the storage device to indicate that the one or more blocks are free for use by the file system to store additional data.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Ganesh Sangle, Chia-Chun Lin, Prabir Paul, Vijayan Satyamoorthy Srinivasa
  • Publication number: 20240069781
    Abstract: An example method for optimizing data deletion in a storage system comprises: monitoring one or more attributes associated with a storage volume associated with a file system; and setting, based on the monitoring of the one or more attributes, a discard option to be either enabled or disabled for the storage volume, wherein when the discard option is enabled, the file system is configured to automatically issue a discard request in response to a request to delete data stored on one or more blocks within a storage device associated with the storage volume, the discard request configured to command the storage device to free the one or more blocks for use by the file system to store additional data; and when the discard option is disabled, the file system does not automatically issue the discard request in response to the request to delete the data.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Prabir Paul, Chia-Chun Lin, Vijayan Satyamoorthy Srinivasa
  • Publication number: 20240068119
    Abstract: A casing structure of electronic device including a metal base plate, a transparent cathodic electrodeposition paints layer, and a transparent paints coating layer is provided. The metal base plate has brushed texture and high gloss surface. The transparent cathodic electrodeposition paints layer is disposed on the base metal base plate. The transparent paints coating layer is disposed on the transparent cathodic electrodeposition paints layer. A manufacturing method of casing structure of electronic device is also provided.
    Type: Application
    Filed: March 2, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Tzu-Wei Lin, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai
  • Publication number: 20240071538
    Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
  • Publication number: 20240071504
    Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE
  • Publication number: 20240071950
    Abstract: Integrated circuit packages and methods of forming the same are discussed. In an embodiment, a device includes: a package substrate; a semiconductor device attached to the package substrate; an underfill between the semiconductor device and the package substrate; and a package stiffener attached to the package substrate, the package stiffener includes: a main body extending around the semiconductor device and the underfill in a top-down view, the main body having a first coefficient of thermal expansion; and pillars in the main body, each of the pillars extending from a top surface of the main body to a bottom surface of the main body, each of the pillars physically contacting the main body, the pillars having a second coefficient of thermal expansion, the second coefficient of thermal expansion being less than the first coefficient of thermal expansion.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Wen-Yi Lin, Kuang-Chun Lee, Chien-Chen Li, Chien-Li Kuo, Kuo-Chio Liu
  • Publication number: 20240071974
    Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Yu-Sheng Lin, Chen-Nan Chiu, Jyun-Lin Wu, Yao-Chun Chuang
  • Publication number: 20240074119
    Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.
    Type: Application
    Filed: May 9, 2023
    Publication date: February 29, 2024
    Inventors: Ren-Chun CHANG, Wei-Chih LIN, Sheng-Chi WU, Wen-Yin TSAI, Li-Hsiu CHEN
  • Patent number: 11916131
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 11916074
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 11916035
    Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: February 27, 2024
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
  • Patent number: 11914887
    Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Han-Wen Hu, Bo-Rong Lin, Huai-Mu Wang
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Publication number: 20240059715
    Abstract: Provided are compounds comprising a first chemical moiety, wherein the first chemical moiety comprises a first heterocyclic ring or a polycyclic fused ring system comprising at least one of the first heterocyclic ring; wherein the first heterocyclic ring comprises at least one Si or Ge atom as the ring atom; wherein in the polycyclic fused ring system, the at least one of the first heterocyclic ring has at most one bond being part of an aromatic ring; wherein the compound further comprises a second chemical moiety; wherein the second chemical moiety is selected from the group consisting of triphenylene, tetraphenylene, carbazole, dibenzothiophene, dibenzofuran, dibenzoselenophene, dibenzofluorene, benzo[d]benzo[4,5]imidazo[1,2-a]imidazole (bimbim), indolocarbazole, indolodibenzothiophene, indolodibenzofuran, indodibenzoselenophene, indolodibenzofluorene, naphthalene, germyl, boryl, amino, pyridine, pyridazine, pyrimidine, pyrazine, triazine, imidazole, benzimidazole, and aza variants thereof; and wherein the
    Type: Application
    Filed: July 6, 2023
    Publication date: February 22, 2024
    Applicant: Universal Display Corporation
    Inventors: Rasha HAMZE, Tyler Fleetham, Hsiao-Fan CHEN, Chun LIN, Elena Sheina
  • Publication number: 20240063294
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Ta-Chun LIN, Jyun-Yang SHEN, Hsiang-Yu LAI, Shih-Chang TSAI, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Publication number: 20240062899
    Abstract: An electronic device and a method for diagnosing heart state based on electrocardiogram (ECG) are provided. An ECG file is obtained, and the ECG file is in a first file format and includes a plurality of potential traces of a plurality of leads. The ECG file is converted to a second file format to obtain electrocardiogram data corresponding to multiple leads. Each potential trace relative to time in the ECG file is converted to the ECG data of each lead. Integrated ECG data associated with the leads is generated based on the ECG data of the plurality of leads through the zero-padding operation and the stacking operation. A diagnostic result of heart status is generated based on the integrated ECG data and a deep learning model.
    Type: Application
    Filed: December 22, 2022
    Publication date: February 22, 2024
    Applicants: Acer Incorporated, Acer Medical Inc., National Health Research Institutes, Chang Gung Memorial Hospital, Keelung
    Inventors: Jun-Hong Chen, Sheng-Wei Chu, Pin-Cyuan Lin, Yi-Chun Lin, Chi-Hsiao Yeh, Ting-Fen Tsai
  • Publication number: 20240061703
    Abstract: A transaction merging method for a first electronic device and a second electronic device. The transaction merging method comprises: (a) receiving a plurality of input transactions from the first electronic device; (b) setting a merge condition of the input transactions according to a transmission condition between the first electronic device and the second electronic device; (c) merging the input transactions according to the merge condition to generate at least one transaction group; and (d) transmitting the transaction group to the second electronic device.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 22, 2024
    Applicant: MEDIATEK INC.
    Inventors: En-Shou Tang, Yuan-Chun Lin, Ming-Lun Hsieh, Chia-Yuan Chang