Patents by Inventor Chun Lin

Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210231570
    Abstract: An inspection apparatus for inspecting a light-emitting diode wafer is provided. The inspection apparatus includes a Z-axis translation stage, a sensing probe, a height measurement module, a carrier, an illumination light source, and a processing device. The sensing probe is integrated with the Z-axis translation stage. The Z-axis translation stage is adapted to drive the sensing probe to move in a Z axis. The sensing probe includes a photoelectric sensor, a beam splitter, and a photoelectric sensing structure. One of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam penetrating the beam splitter, and the other one of the photoelectric sensor of the sensing probe and the height measurement module is adapted to receive a light beam reflected by the beam splitter. The carrier is configured to carry the light-emitting diode wafer. The illumination light source is configured to emit an illumination beam to irradiate the light-emitting diode wafer.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 29, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Yan-Rung Lin, Chih-Hsiang Liu, Chung-Lun Kuo, Hsiang-Chun Wei, Yeou-Sung Lin, Chieh-Yi Lo
  • Publication number: 20210235572
    Abstract: A system includes a laser source operable to provide a laser beam, a laser amplifier having a gain medium operable to provide energy to the laser beam when the laser beam passes through the laser amplifier, and a residual gain monitor operable to provide a probe beam and operable to derive a residual gain of the laser amplifier from the probe beam when the probe beam passes through the laser amplifier while being offset from the laser beam in time or in path.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Chun-Lin Louis Chang, Jen-Hao Yeh, Han-Lung Chang, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Publication number: 20210228732
    Abstract: Pharmaceutical composition comprising antibodies or antigen binding fragments thereof that bind to stage-specific embryonic antigen 4 (SSEA-4) are disclosed herein, as well as methods of use thereof. Methods of use include, without limitation, cancer therapies and diagnositcs. The antibodies of the disclosure can bind to certain cancer cell surfaces. Exemplary targets of the antibodies disclosed herein can include carcinomas, such as breast cancer, lung cancer, esophageal cancer, rectal cancer, biliary cancer, liver cancer, buccal cancer, gastric cancer, colon cancer, nasopharyngeal cancer, kidney cancer, prostate cancer, ovarian cancer, cervical cancer, endometrial cancer, pancreatic cancer, testicular cancer, bladder cancer, head and neck cancer, oral cancer, neuroendocrine cancer, adrenal cancer, thyroid cancer, bone cancer, skin cancer, basal cell carcinoma, squamous cell carcinoma, melanoma, and/or brain tumor.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 29, 2021
    Inventors: Cheng-Der Tony YU, Jiann-Shiun LAI, I-Ju CHEN, Chiu-Chun LIN
  • Publication number: 20210233803
    Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Yu-Sheng TANG, Fu-Chen CHANG, Cheng-Lin HUANG, Wen-Ming CHEN, Chun-Yen LO, Kuo-Chio LIU
  • Patent number: 11075164
    Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
  • Patent number: 11074366
    Abstract: A masking system and method for automatically masking sensitive user information on a webpage is provided. The method includes the steps of identifying a location of the first user data of the first type of sensitive user information on the webpage, updating an initial path to the first user data to account for changes to the initial path detected in response to repeated visits to the webpage, wherein the updated initial path to the first user data is stored as a stable path, locating a second user data associated with a second type of sensitive user information on the webpage, by accessing a central database containing path information to a location of the second user data on the webpage, and masking the first user data and the second user data on the webpage, using the stable path and the path information obtained from the central database.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ching-Wei Cheng, Tzu-Ching Kuo, June-Ray Lin, Yi-Chun Tsai
  • Patent number: 11071711
    Abstract: Skin care compositions are provided which contain Thermus thermophilus ferment and silybin and provide anti-aging and reparative effect for skin. The compositions may also include one or more additional substances selected from carnosine, adenosine and CG-EDP3. The substances are dispersed in an aqueous carrier, such as water, to be applied to the skin in a spreadable form.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 27, 2021
    Inventors: Yi-Chun Lin, Marc Cornell, Gregory Bays Brown, Elizabeth Myra Martin
  • Patent number: 11075079
    Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20210223709
    Abstract: The present disclosure describes a lithography apparatus comprising a photoresist coating unit configured to perform one or more coating processes on a substrate. The lithography apparatus further comprises a detection unit configured to determine a contamination level of a contaminant from the one or more coating processes adheres on a sidewall of the lithography apparatus. The lithography apparatus further comprises a controller unit configured to adjust one or more operations of the lithography apparatus based on a comparison between the contamination level and a baseline cleanliness requirement of the lithography apparatus.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Chun Hsieh, Chih-Che Lin, Pei-Yi Su
  • Publication number: 20210223516
    Abstract: An image capturing optical lens assembly includes five lens elements, in order from an object side to an image side along an optical path, being a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fourth lens element with positive refractive power has an image-side surface being convex in a paraxial region thereof. The fifth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. At least one of surfaces of the fifth lens element includes at least one critical point in an off-axis region thereof.
    Type: Application
    Filed: August 13, 2020
    Publication date: July 22, 2021
    Inventors: Cheng-Chen LIN, Kuan-Chun WANG, Tzu-Chieh KUO
  • Publication number: 20210226530
    Abstract: A switching power conversion circuit includes a conversion capacitor, a capacitive power conversion circuit, an inductor, an inductive power conversion circuit and a switching control circuit. The capacitive power conversion circuit includes plural switching devices for generating an intermediate voltage which is in a predetermined proportional relationship to the input voltage. The inductive power conversion circuit includes plural switching devices for converting the intermediate voltage to an output voltage. The plural switching devices of the capacitive power conversion circuit and the inductive power conversion circuit switch the conversion capacitor and the inductor periodically according to the duty ratio of the switching control signal generated by the switching control circuit. The capacitive power conversion circuit and the inductive power conversion circuit share one of the plural switching devices.
    Type: Application
    Filed: September 16, 2020
    Publication date: July 22, 2021
    Inventors: Shui-Mu Lin, Tsung-Wei Huang, Huan-Chien Yang, Yung-Chun Chuang
  • Publication number: 20210225839
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw, Shien-Yang Wu
  • Publication number: 20210223821
    Abstract: An electronic device assembly is provided, including an electronic device body and a detachable lens module. The electronic device body has a housing and a first joining unit, wherein the first joining unit is disposed on the housing. The detachable lens module is detachably assembled onto the housing and has a second joining unit, wherein the first joining unit is joined to the second joining unit to electrically connect the detachable lens module to the electronic device body.
    Type: Application
    Filed: June 19, 2020
    Publication date: July 22, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai, Chi-Hung Lai, Wu-Chen Lee, Pin-Chueh Lin, Chih-Wei Liao, Ting-Wen Pai, Wen-Chieh Chen
  • Publication number: 20210226047
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 22, 2021
    Inventors: YAO-CHUNG CHANG, PO-CHIH CHEN, JIUN-LEI JERRY YU, CHUN LIN TSAI
  • Patent number: 11069558
    Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
  • Patent number: 11069731
    Abstract: According to one example, a device includes a semiconductor substrate. The device further includes a plurality of color filters disposed above the semiconductor substrate. The device further includes a plurality of micro-lenses disposed above the set of color filters. The device further includes a structure that is configured to block light radiation that is traveling towards a region between adjacent micro-lenses. The structure and the color filters are level at respective top surfaces and bottom surfaces thereof.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Lin, Ching-Chun Wang, Dun-Nian Yaung, Chun-Ming Su, Tzu-Hsuan Hsu
  • Patent number: 11065814
    Abstract: The present application provides not only a heating device for additive manufacturing but also a heating module and a manufacturing apparatus utilizing the heating device. The heating device utilizes a rotational reflective cover to modulate a heating direction of a heating source, which expands an area correspondingly irradiated by the heating source and enhances uniformity of heating. Besides, the heating modules can be coupled and controlled by a controlling subsystem so as to respectively irradiate different areas with ranges at least partially intersecting each other, which also improves heating uniformity for heating a large area.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 20, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chung-Chun Huang, Chih-Peng Chen, Po-Shen Lin
  • Patent number: 11069785
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11069805
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
  • Patent number: D925479
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 20, 2021
    Assignee: CHYNG HONG ELECTRONIC CO., LTD.
    Inventor: Mu-Chun Lin