Abstract: A pixel array may include a plurality of pixel regions including a first pixel region and a second pixel region. The pixel array may include a metal grid structure over the plurality of pixel regions. The pixel array may include a light blocking layer. A first portion of the light blocking layer may be over the first pixel region and under the metal grid structure. The first portion may have a first thickness. A second portion of the light blocking layer may be over the second pixel region and under the metal grid structure. The second portion may have a second thickness that is different from the first thickness.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: A method of fabricating a semiconductor device includes providing a partially-fabricated semiconductor device including a dummy gate structure disposed over a semiconductor layer stack. In some embodiments, the method further includes removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further includes forming one or more refill layers in a bottom portion of the trench and forming one or more refill layers in a top portion of the trench over the bottom portion of the trench. In some embodiments, the one or more refill layers in the top and bottom portions of the trench respectively define top and bottom portions of an isolation structure. In some examples, at least one refill layer of respective ones of the top and bottom portions of the isolation structure have a different material composition.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Abstract: A verification method is provided. The verification method may be applied to an apparatus. The verification method may include the following steps. The apparatus may generate a first random nonce. Then, the apparatus may bind the first random nonce to the signing data. Then, the apparatus may calculate the first signature according to the hash-based post-quantum cryptography (PQC) algorithm and the signing data bound to the first random nonce to obtain the first verification time. Then, the apparatus may determine whether the first verification time meets the quality of service (QOS) condition. The apparatus may adopt the first signature for a verification process in response to the first verification time meeting the QoS condition.

Abstract: An electrical connector includes an insulation body, a terminal assembly, a middle grounding plate and two shielding plates. The terminal assembly is fastened in the insulation body. The terminal assembly has a base portion, and a plurality of terminals fastened in the base portion. The plurality of the terminals are arranged in two rows. The plurality of the terminals arranged in each row have two grounding terminals. Each grounding terminal has a fastening portion. A middle of the fastening portion is bent inward and frontward to form an arc portion. An outer surface of the arc portion extends outward, then is bent outward and extends outward to form a grounding foot. The middle grounding plate is mounted in a middle of the terminal assembly. The two shielding plates are disposed to an upper surface and a lower surface of the insulation body.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes first inner spacers formed between the first gate structure and the first source/drain epitaxial structures. The structure also includes second nanostructures formed over the first nanostructures. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The structure also includes second inner spacers formed between the second gate structure and the second source/drain epitaxial structures. The first inner spacers and the second inner spacers have different widths.

Abstract: A method of forming a semiconductor structure includes forming a fin structure over a substrate; forming first and second source/drain trenches in the fin structure; forming first and second SiGe layers in the first and second source/drain trenches, respectively; and forming first and second source/drain features over the first and second SiGe layers in the first and second source/drain trenches, respectively. The method further includes forming a first interlayer dielectric (ILD) layer on a backside of the substrate; etching the first ILD layer and the substrate to form a first opening that exposes the first SiGe layer; removing the first SiGe layer to form a second opening that exposes the first source/drain feature; and depositing a conductive material in the first and second openings to form a first source/drain contact. The lateral dimensions of the first opening are greater than those of the second opening.

Abstract: A multifunctional reconfigurable reflectarray structure (RRA) includes a radiation layer and a direct current bias layer. The radiation layer includes a first metal member, a second metal member, a first diode and a second diode. The first diode is connected between the first metal member and the second metal member. The second diode is coupled to the second metal member. The direct current bias layer is connected to the first diode and the second diode. A first working state of the first diode and a second working state of the second diode are controlled by a first input signal and a second input signal. The radiation layer is modulated according to the first working state and second working state, so that an electromagnetic wave forms one of a single-beam reflection and a dual-beam reflection after being incident on the radiation layer, or is absorbed by the radiation layer.

Abstract: A semiconductor structure includes a first transistor, a second transistor, and a gate structure. The first transistor includes first nanostructures and first source/drain features. The first nanostructures are spaced apart from each other in a Z-direction. The first source/drain features are on opposite sides of the first nanostructures in an X-direction. The second transistor includes second nanostructures and second source/drain features. The second nanostructures are spaced apart from each other in the Z-direction. The second nanostructures are over the first nanostructures. The second source/drain features are on opposite sides of the second nanostructures in the X-direction. The second source/drain features are over the first source/drain features. The gate structure wraps around the first nanostructures and the second nanostructures. A thickness of middle portions of the first nanostructures is greater than a thickness of middle portions of the second nanostructures.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Abstract: A semiconductor structure includes a first semiconductor device formed in a first device region of a substrate. The first semiconductor device includes a first gate structure comprising a first spacer layer, wherein the first spacer layer has a first thickness. The first semiconductor device also includes a first conductive feature disposed over a first source/drain feature, and the first conductive feature has a first width. The semiconductor structure further includes a second semiconductor device formed in a second device region of the substrate. The second semiconductor device includes a second gate structure comprising a second spacer layer, wherein the second spacer layer has a second thickness different than the first thickness. The second semiconductor device also includes a second conductive feature disposed over a second source/drain feature, and the second conductive feature has a second width different than the first width.

Abstract: A semiconductor device includes a first stacked structure, a second stacked structure, a first vertical connector, and a second vertical connector. The first stacked structure includes a first stacked wafer and a first bonding layer. The first stacked wafer includes multiple first dielectric bonding interfaces. The second stacked structure includes a second stacked wafer and a second bonding layer. The second stacked wafer includes multiple second dielectric bonding interfaces. The first bonding layer is bonded and electrically connected to the second bonding layer, such that there is a hybrid bonding interface between the first stacked structure and the second stacked structure. The first vertical connector penetrates the first dielectric bonding interfaces and is electrically connected to the first bonding layer. The second vertical connector penetrates the second dielectric bonding interfaces and is electrically connected to the second bonding layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region and a gate structure extending into the substrate, wherein a portion of the gate structure below a top surface of the substrate abuts the isolation region. An associated method for fabricating the semiconductor structure is also disclosed.

Abstract: A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

Abstract: A wafer structure and a manufacturing method thereof are provided. The wafer structure includes a substrate structure, a first dielectric layer, multiple test pads, a second dielectric layer, and multiple bond pads. The first dielectric layer is disposed on the substrate structure. The test pads are disposed in and exposed outside the first dielectric layer. Each test pad has a probe mark. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a top surface away from the test pads. Multiple bond pads are disposed in and exposed outside the second dielectric layer. Each bond pad is electrically connected to the corresponding test pad. The bond pads have bonding surfaces away from the test pads. The bonding surfaces are flush with the top surface. In the normal direction of the substrate structure, each bond pad does not overlap the probe mark of the corresponding test pad.

Abstract: A memory device has a memory cell operated in a first power domain having a first voltage level. A memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. A word line decoder circuit is operated in the first power domain, and a word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. An IO circuit is connected to the memory bit line, and the IO circuit is operated in a second power domain having a second voltage level lower than the first voltage level. A tracking word line is connected to a tracking cell, and the tracking word line is configured to output a tracking cell enable signal in the first power domain. A tracking bit line is connected to the tracking cell, and the tracking bit line is configured to output a trigger signal in the first power domain to the IO circuit.