Patents by Inventor Chun Lin

Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096917
    Abstract: An image sensor structure includes a semiconductor substrate, a plurality of image sensing elements, a reflective element, and a high-k dielectric structure. The image sensing elements are in the semiconductor substrate. The reflective element is in the semiconductor substrate and between the image sensing elements. The high-k dielectric structure is between the reflective element and the image sensing elements.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: PO CHUN CHANG, PING-HAO LIN, WEI-LIN CHEN, KUN-HUI LIN, KUO-CHENG LEE
  • Publication number: 20240096781
    Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
  • Patent number: 11936418
    Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 19, 2024
    Assignee: KAIKUTEK INC.
    Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Mohammad Athar Khalil, Wen-Sheng Cheng, Chen-Lun Lin, Chin-Wei Kuo, Ming Wei Kung, Khoi Duc Le
  • Patent number: 11936138
    Abstract: An electronic device includes a first main body, a first electrical connector, and an insert member. The first main body has an insertion end and one or more holes located at the insertion end. The first electrical connector is disposed at the insertion end. The insert member is coupled to the first main body through the one or more holes and includes a plurality of ribs and a plurality of removed portions. Each of the ribs extends away from the insertion end. The ribs and the removed portions are sequentially and linearly arranged according to a coding pattern.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Cheng-Chun Lin
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Patent number: 11931187
    Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 19, 2024
    Assignees: Chang Gung Medical Foundation Chang Gung Memorial Hospital at Keelung, Chang Gung Memorial Hospital, Linkou, Chang Gung University
    Inventors: Jiun-Jie Wang, Yi-Hsin Weng, Shu-Hang Ng, Jur-Shan Cheng, Yi-Ming Wu, Yao-Liang Chen, Wey-Yil Lin, Chin-Song Lu, Wen-Chuin Hsu, Chia-Ling Chen, Yi-Chun Chen, Sung-Han Lin, Chih-Chien Tsai
  • Patent number: 11937371
    Abstract: A radio frequency (RF) system and a communication device are provided. The RF system includes a flexible circuit board, a first antenna module and a RF module. The flexible circuit board has a first surface and a second surface, and the first surface and the second surface are located at different sides of the flexible circuit board. The first antenna module is disposed on the first surface of the flexible circuit board. The first antenna module includes a first carrier, a first antenna element disposed on or in the first carrier, and a first conductive member between the first carrier and the flexible circuit board. The RF module is disposed on the second surface of the flexible circuit board and electrically connected to the first antenna module.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 19, 2024
    Assignee: MEDIATEK INC.
    Inventors: Wun-Jian Lin, Chung-Hsin Chiang, Yeh-Chun Kao, Shih-Huang Yeh
  • Patent number: 11934585
    Abstract: A method for performing interactive operation upon a stereoscopic image and a stereoscopic image display system are provided. The stereoscopic image display system includes a stereoscopic display and a gesture sensor. In the method, the stereoscopic display displays the stereoscopic image, and the gesture sensor senses a gesture. A current gesture state is obtained. A previous state of the stereoscopic image and a previous gesture state are obtained. Stereo coordinate variations corresponding to the gesture can be calculated according to the current gesture state and the previous gesture state. New stereoscopic image data can be obtained according to the previous state of the stereoscopic image and the stereo coordinate variations corresponding to the gesture. The stereoscopic display is used to display a new stereoscopic image that is rendered from the new stereoscopic image data.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: March 19, 2024
    Assignee: LIXEL INC.
    Inventors: Arvin Lin, Yung-Cheng Cheng, Chun-Hsiang Yang
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240085614
    Abstract: An anti-peep light source module includes a light source module and a viewing angle switching module. The light source module has a light source and a light guide plate (LGP) and has light emitting elements arranged along a first direction. The viewing angle switching module is located on a transmission path of an illumination beam of the light source module and includes a viewing angle limiting element and a viewing angle adjusting element configured to change a viewing angle of the illumination beam. The viewing angle limiting element has a grating structure and is located between the viewing angle adjusting element and the light source module. an included angle between an extension direction of the grating structure and the first direction is within a range from 88 degrees to 92 degrees. The anti-peep light source module and A display device achieve favorable optical performance, user experience, and production yield.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Applicant: Coretronic Corporation
    Inventors: Yi-Cheng Lin, Chih-Hsuan Kuo, Sung-Chun Hsu, Ming-Hsiung Fan, Tzeng-Ke Shiau
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240088227
    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Chun-I WU, Huang-Lin CHAO
  • Publication number: 20240083555
    Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The waste collection device includes a fluid ejection element, and the flow out of the fluid ejection element flows toward a space where waste is collected.
    Type: Application
    Filed: May 12, 2023
    Publication date: March 14, 2024
    Inventors: Wei-Chun LIU, Ching-Fu WANG, Cheng-Che HO, Huan-Fu LIN
  • Publication number: 20240088278
    Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Chun-Wing YEUNG, Chih-Hao CHANG
  • Publication number: 20240087962
    Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
  • Publication number: 20240088564
    Abstract: A transmission device with a phase-adjustment function includes a first dielectric layer, a signal line, a ground plane, and a first parasitic element. The first dielectric layer has a first surface and a second surface which are opposite to each other. The signal line is disposed on the first surface of the first dielectric layer. The ground plane is disposed on the second surface of the first dielectric layer. The first parasitic element is coupled to a first connection point on the signal line. The first parasitic element is configured to provide a first delay phase.
    Type: Application
    Filed: August 11, 2023
    Publication date: March 14, 2024
    Inventor: Chun-Lin HUANG
  • Publication number: 20240084370
    Abstract: The disclosure provides a kit for detecting microsatellite instability and a method therefor. The kit includes a negative control, a plurality of qPCR reaction solutions, a qPCR premix and a sterile enzyme-free water; the plurality of qPCR reaction solutions includes 6 pairs of upstream primers and downstream primers of which the MSI mutation site is amplified, and a reference probe for the internal reference and a detection probe for the mutation site. The difference between the amplification of the gene and the gene at the mutation site of the samples and the negative control is used to detect the microsatellite instability. The method and kit as provided is easy and simple without the need of normal tissues being a control, and the need to open the cap. By doing so, aerosol pollution is avoided and sample supplies are conserved.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 14, 2024
    Inventors: Chun MENG, Jing HONG, Liang GUO, Wenxiao MA, Yiwei HUANG, Xiaodie LIN, Liling XIE, Xiaoya WANG, Qixin LIN
  • Publication number: 20240088053
    Abstract: A semiconductor structure includes a first dielectric layer, a first die, a second die, a first molding, and a second molding. The first die is disposed under the first dielectric layer, and has a first surface facing the first dielectric layer and a second surface opposite to the first surface. The second die is disposed over the first dielectric layer, and has a third surface facing the first dielectric layer and a fourth surface opposite to the third surface. The first molding encapsulates the first die. The second molding is disposed over the first die and the first dielectric layer. The first surface of the first die and the third surface of the second die are in contact with the first dielectric layer. The fourth surface of the second die is partially exposed through the second molding and partially covered by the second molding.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: CHEN-HUA YU, KAI-CHIANG WU, CHUN-LIN LU
  • Publication number: 20240088001
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
  • Publication number: 20240086609
    Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 14, 2024
    Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN