Patents by Inventor Chun-Lin Tsai

Chun-Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Publication number: 20200098517
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: March 26, 2020
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20200091007
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.
    Type: Application
    Filed: February 15, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chu-An LEE, Chen-Hao WU, Peng-Chung JANGJIAN, Chun-Wen HSIAO, Teng-Chun TSAI, Huang-Lin CHAO
  • Publication number: 20200083324
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a channel layer disposed over a substrate and including a first material. An active layer is over the channel layer and includes a second material different than the first material. An isolation structure has a horizontally extending segment that is below the channel layer and one or more vertically extending segments that are directly over the horizontally extending segment. One or more contacts extend through the channel layer and the active layer to contact the one or more vertically extending segments.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Publication number: 20200058647
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200043912
    Abstract: Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 6, 2020
    Inventors: Ker Hsiao Huo, Fu-Chih Yang, Chun Lin Tsai, Yi-Min Chen, Chih-Yuan Chan
  • Publication number: 20200044014
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200032105
    Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including one or more oxygen molecules, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 30, 2020
    Inventors: An-Hsuan Lee, Shen-Nan Lee, Chen-Hao Wu, Chun-Hung Liao, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20200035625
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20200027874
    Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Ker Hsiao Huo, Fu-Chih Yang, Chun Lin Tsai, Yi-Min Chen, Chih-Yuan Chan
  • Patent number: 10542504
    Abstract: A wireless communication system and method is provided. The wireless communication system includes a wireless transceiver device and a processing device. The processing device includes a direction control module, a power adjusting module and a boundary setting module. The direction control module controls the scanning direction and generates a point direction information record according to each reference position respectively. The power adjusting module adjusts the transmitting power and generates a point power information record according to each reference position and the corresponding point direction information record respectively. The boundary setting module generates a boundary information record. The processing device controls the transmitting direction and the transmitting power according to the point direction information record(s), the point power information record(s) and the boundary information record, so as to limit a transmission of the wireless signal within a specific area.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 21, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yin-Chang Liu, Hsuan-Lin Cheng, Chih-Wei Wang, Chun-Yi Lu, Ya-Chen Chuang, Chia-Yu Chen, Tsung-Han Tsai
  • Patent number: 10535730
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20200006674
    Abstract: Organic light emitting materials and devices comprising phosphorescent metal complexes comprising ligands comprising aryl or heteroaryl groups substituted at both ortho positions are described. An organic light emitting device, comprising: an anode, a hole transport layer; an organic emissive layer comprising an emissive layer host and an emissive dopant; an electron impeding layer; and electron transport layer; and a cathode disposed, in that order, over a substrate.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 2, 2020
    Applicant: Universal Display Corporation
    Inventors: Chun LIN, Peter B. MACKENZIE, Robert W. WALTERS, Jui-Yi TSAI, Cory S. BROWN, Jun DENG
  • Publication number: 20200002161
    Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
    Type: Application
    Filed: August 19, 2019
    Publication date: January 2, 2020
    Inventors: Chun-wen CHENG, Hung-Chia TSAI, Lan-Lin CHAO, Yuan-Chih HSIEH, Ping-Yin LIU
  • Patent number: 10522618
    Abstract: An isolation structure for active devices is provided. In some embodiments, the isolation structure is used in a transistor. The transistor includes a substrate having a first doping type. The transistor also includes a channel layer positioned over the substrate and comprising a first section and a second section. The transistor further includes an active layer positioned over the channel layer. The isolation structure includes a horizontal segment, a first vertical segment, and a second vertical segment. The horizontal segment is arranged below the second section of the channel layer and continuously extends between the first vertical segment and the second vertical segment. The isolation structure has a second doping type that is different than the first doping type.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
  • Patent number: 10522671
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
  • Publication number: 20190390108
    Abstract: Novel Iridium complexes having three different bidentate ligands useful for phosphorescent emitters in OLEDs are disclosed. At least one of the three different bidentate ligands is a carbene ligand.
    Type: Application
    Filed: September 7, 2019
    Publication date: December 26, 2019
    Applicant: Universal Display Corporation
    Inventors: Jui-Yi TSAI, Chuanjun XIA, Chun LIN, Adrian U. PALACIOS, Enrique OÑATE, Miguel A. Esteruelas, Pierre-Luc T. BOUDREAULT, Sonia BAJO, Montserrat OLIVÁN
  • Patent number: 10510882
    Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10483259
    Abstract: Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Fu-Chih Yang, Chun Lin Tsai, Yi-Min Chen, Chih-Yuan Chan
  • Publication number: 20190341563
    Abstract: Compounds comprising phosphorescent metal complexes comprising cyclometallated imidazo[1,2-f]phenanthridine and diimidazo[1,2-a:1?,2?-c]quinazoline ligands, or isoelectronic or benzannulated analogs thereof, are described. Organic light emitting diode devices comprising these compounds are also described.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Applicant: Universal Display Corporation
    Inventors: David KNOWLES, Chun LIN, Peter MACKENZIE, Jui-Yi TSAI, Robert W. WALTERS, Scott BEERS, Cory S. BROWN, Walter YEAGER