Abstract: A method for fabricating an interconnect structure is disclosed. A substrate with a first dielectric layer is provided. A first conductor is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the top surface of the first conductor. An annealing process is performed on the top surface of the first conductor. The annealing process includes the conditions of a temperature of 400-450° C., duration less than 5 minutes, and gaseous atmosphere comprising hydrogen and nitrogen.

Abstract: The present disclosure provides a preparation method of setmelanotide by cyclization of a disulfide bond in a solid phase. By using different solvents or mixed solvents to carry out a cyclization reaction in a solid phase, the reaction concentration can be greatly increased in comparison with a cyclization reaction in a liquid phase, and the production of impurities can also be reduced, so that the effects of reducing the use of the solvents and increasing the production capacity are achieved.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining smoothness of the waveform segments; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the waveform segments, and generating a detection result.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining systolic peaks for determining first and second portions of the waveform segments; determining smoothness of the second portions; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the second portions, and generating a detection result.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

Abstract: A method for detecting a location of a segment of a feeding tube is provided. The feeding tube has a proximal end, a hollow tube body and a distal end, and is placed inside the body of a patient. An audio collecting component is placed on a predetermined part of the patient. The method includes steps of pumping air into the proximal end of the feeding tube, collecting sound to obtain audio data by the audio collecting component, performing audio analysis on the audio data, and determining whether a segment of the hollow tube body is at a part inside the body of the patient that corresponds with the location of the audio collecting component based on result of the audio analysis.

Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.