Patents by Inventor Chun-Ling Lin

Chun-Ling Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210157369
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20200168450
    Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Kuan-Hsiang Chen, Hsin-Fu Huang, Chun-Ling Lin, Sheng-Yi Su, Pei-Hsun Kao
  • Patent number: 10446489
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10323332
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Publication number: 20190067184
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10153231
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Patent number: 10079177
    Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 18, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
  • Publication number: 20180261537
    Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 13, 2018
    Inventors: Ko-Wei Lin, Hung-Miao Lin, Chun-Ling Lin, Ying-Lien Chen, Huei-Ru Tsai, Sheng-Yi Su
  • Publication number: 20180138263
    Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Ko-Wei Lin, Yen-Chen Chen, Chin-Fu Lin, Chun-Yuan Wu, Chun-Ling Lin
  • Patent number: 9966425
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
  • Patent number: 9685316
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Publication number: 20160319450
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Application
    Filed: July 11, 2016
    Publication date: November 3, 2016
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Publication number: 20160276215
    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises steps as follows. At least one trench is provided in a low-k dielectric layer on a substrate. The trench is filled with a copper (Cu) film. Pure cobalt (Co) is deposited on a surface of the Cu film by introducing a flow of a carrier gas carrying a Co-containing precursor and a reducing agent onto the surface of the Cu film. The flowrate of the flow is within a range from 5 to 19 sccm.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: PEI-TING LEE, GUO-WEI CHEN, CHUN-LING LIN, CHI-MAO HSU, CHING-WEI HSU, HUEI-RU TSAI, JIA-RONG LI, SHANG NAN CHOU, PO CHIH WU
  • Patent number: 9416459
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Patent number: 9412653
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Patent number: 9318338
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin
  • Publication number: 20150340280
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Patent number: 9136170
    Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chun-Ling Lin, Huei-Ru Tsai, Ching-Wei Hsu, Chin-Fu Lin, Hsin-Yu Chen
  • Patent number: 9000568
    Abstract: A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Yu-Ren Wang, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Te-Lin Sun
  • Publication number: 20150050799
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (PO-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin