Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered.

Abstract: The present invention provides a glasses construction including: an auxiliary frame coupled with optical lenses and disposed as needed behind the middle portion of a glasses frame coupled with lenses; and a protective frame disposed behind and snap-engaged with the glasses frame. The glasses frame and the protective frame together limit the position of the auxiliary frame. Two connecting elements pivotally disposed on two sides of the glasses frame, respectively, are snap-engaged with connecting members extending from the ends of two temples and stopping portions formed beside the connecting members to thereby form a glasses construction. Hence, the combination or separation between the glasses frame and the protective frame, between the glasses frame and the auxiliary frame, or between two said connecting elements pivotally disposed on two sides of the glasses frame and the temples is advantageously characterized by quick positioning or removal by convenient operation.

Abstract: A clock system includes a clock signal generating circuit and a controlling circuit. The clock signal generating circuit is used for generating a primary clock signal and a reference clock signal both derived from an oscillating signal of the clock signal generating circuit. The controlling circuit is coupled to the clock signal generating circuit and used for receiving the primary clock signal under a normal mode and compensating timing information generated from the primary clock signal according to the reference clock signal when the clock system exits a power saving mode. The primary clock signal is de-activated when the clock system enters the power saving mode and is activated when the clock system exits the power saving mode. The clock system can keep a continue clock for system to use when the primary clock signal is gated or power saving mode is entered.

Abstract: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

Abstract: A configurable calculating circuit includes a multiplexer, a mixer and an accumulator. The multiplexer is for receiving input signals including at least a first and a second input signals, and selectively outputting at least one of the input signals. The mixer is for mixing a selected input signal outputted from the multiplexer with a local oscillation signal to generate a mixed signal. The accumulator is for accumulating the mixed signal to generate an accumulated signal. When the configurable calculating circuit is operated under a first mode, the multiplexer selects the first input signal, and the accumulator performs a first accumulating operation upon the mixed signal; and when the configurable calculating circuit is operated under a second mode, the multiplexer selects the second input signal, and the accumulator performs a second accumulating operation, different from the first accumulating operation, upon the mixed signal.

Abstract: A signal processing apparatus includes a signal generating block arranged to generate a target estimated signal of a specific signal component in an input signal. The signal generating block includes a reference signal generating circuit, a signal processing circuit, and a signal adjusting circuit. The reference signal generating circuit is arranged to generate a reference estimated signal for the specific signal component in the input signal. The signal processing circuit is coupled to the reference signal generating circuit, and arranged to process the reference estimated signal and accordingly generate a signal processing result. The signal adjusting circuit is coupled to the signal processing circuit and the reference signal generating circuit, and arranged to output the target estimated signal by adjusting the reference estimated signal according to the signal processing result.

Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: A configurable calculating circuit includes a multiplexer, a mixer and an accumulator. The multiplexer is for receiving input signals including at least a first and a second input signals, and selectively outputting at least one of the input signals. The mixer is for mixing a selected input signal outputted from the multiplexer with a local oscillation signal to generate a mixed signal. The accumulator is for accumulating the mixed signal to generate an accumulated signal. When the configurable calculating circuit is operated under a first mode, the multiplexer selects the first input signal, and the accumulator performs a first accumulating operation upon the mixed signal; and when the configurable calculating circuit is operated under a second mode, the multiplexer selects the second input signal, and the accumulator performs a second accumulating operation, different from the first accumulating operation, upon the mixed signal.

Abstract: An address-accessing device includes first and second information generators for producing first and second information according to the received address signals; a phase offset detector for producing a phase offset according to the first and second information; a reference signal generator for producing a reference signal according to the phase offset, the first information and the second information; and a decoder used to determine the structure type of an address-in-pregroove unit (ADIP) according to the reference value. This address-accessing device is capable of adjusting the decision level and the phase offset automatically to lower the error rate occurring in the address access procedure.

Abstract: A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals transmitted from a first transmitter system through a first carrier frequency and a second transmitter system through a second carrier frequency respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.

Abstract: A GNSS receiver and method for GNSS memory code generation are disclosed. The GNSS receiver comprises a buffer, a correlator, and a selector. The buffer receives and stores a plurality of first code segments. Each of the first code segment is at least a portion of a memory code. The selector selects a selecting window of the first code segments stored in the buffer as a second code segment according to the code phase selection signal. The correlator calculates a correlation between a received GNSS signal and the second code segment.

Abstract: An adaptive time-division multiplexing receiver and method for a GNSS system using pilot and data channels for each satellite are disclosed. According to the present invention, multiplexing hypotheses of correlation are properly distributed to pilot and data channels. The pilot and data channels of one satellite can be dealt with as two satellites. Alternatively, correlation is mainly executed to the pilot channel. After the pilot channel is acquired, information such as code phase and Doppler frequency of the satellite are known. Therefore, the data can be demodulated based on the known information.

Abstract: The invention is a methodology which makes it possible to select from a very large number of cells, a single cell or cells of interest and obtain specific information from those cells in a rapid and efficient manner. As an example of the methodology, a large number of antibody producing cells such as plasma cells are separated so that these individual antibody producing plasma cells are placed in individual wells. The cells are allowed to produce antibodies and the antibodies in the wells are then contacted with a protein bound to a solid surface such as a well top. The protein universally and specifically binds antibodies in the wells. The surface or well tray top includes addresses configured such that each address is specifically related to one of the individual wells containing a cell producing antibodies.

Abstract: A shared memory device for a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The shared memory device has a memory space, allocated to be commonly shared by the first functional stage and the second functional stage, for buffering processing data generated from the first functional stage or the second functional stage.

Abstract: The invention provides a Global Navigation Satellite System (GNSS) receiver. In one embodiment, the GNSS receiver comprises a memory, a buffer, a correlator, and a selector. The memory stores a memory code and outputs a portion of the memory code as a first code segment. The buffer comprises a plurality of component buffers and stores the first code segment into one of the component buffers in order. The selector selects a portion of the first code segments stored in the buffer as a second code segment output to the correlator according to the code phase selection signal, wherein the data length of the second code segment is equal to a correlation data length of the correlator. The correlator calculates a correlation between a received GNSS signal with the correlation data length and the second code segment.

Abstract: A satellite signal adaptive time-division multiplexing receiving device is disclosed. The receiving device operates in time-division multiplexing distributed for various domains such as satellite number, Doppler frequency, code phase and accuracy. When some specific time slots of the time-division multiplexing distribution are unnecessary to be searched, the receiving device uses a disable signal to deactivate specific components such as correlator and memory thereof during those time slots to reduce power consumption.