Patents by Inventor Chun On To

Chun On To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240177088
    Abstract: A deciding system for stopping and dispatching vehicles includes a memory and a cloud processing unit. The cloud processing unit is configured to determine one of a fixed vehicle dispatching algorithm and a non-fixed vehicle dispatching algorithm to be executed by the cloud processing unit according to a temporary car-hailing order message; execute the one of the fixed vehicle dispatching algorithm and the non-fixed vehicle dispatching algorithm to generate a stop message corresponding to a stop station according to a dispatch parameter set from the memory, and generate a stop number set corresponding to the first vehicle according to the stop message; and execute the one of the fixed vehicle dispatching algorithm and the non-fixed vehicle dispatching algorithm to generate a dispatch message according to the dispatch parameter set, and generate a dispatch vehicle number set corresponding to the second vehicle according to the dispatch message.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: I-Chun KUO, Cheng-Hsien WANG, Tsung-Ming HSU, Ming-Kuan KO
  • Publication number: 20240178847
    Abstract: The present disclosure discloses a media communication apparatus having built-in signal synchronization mechanism. A local clock generation circuit generates a reference clock signal and a media clock signal. A time calibration circuit performs time calibration process with an external apparatus to generate time calibration information to further calibrate the reference clock signal and the media clock signal accordingly to generate a calibrated reference clock signal and a calibrated media clock signal on a standard time domain. A media clock processing circuit generates a sampling signal according to the calibrated media clock signal. A signal processing circuit generates time related information according to the calibrated reference clock signal to process an input media signal according to the time related information and the sampling signal and generate an output media signal.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 30, 2024
    Inventors: MING-JHE DU, Ming-Hsuan Tsai, Chun-I Yeh, Yu-Chong Yen
  • Publication number: 20240177887
    Abstract: A core wire includes: an inner conductor; and an insulating layer covering the inner conductor, wherein the insulation layer is made by 3D printing process, the insulating layer includes a first semi-insulating layer and a second semi-insulating layer, each of the first semi-insulating layer and the second semi-insulating layer has a groove that matchingly accommodates the shape of the inner conductor, and the first semi-insulating layer and the second semi-insulating layer are combined together.
    Type: Application
    Filed: November 25, 2023
    Publication date: May 30, 2024
    Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: CHUN-LIN LEE, Jian-Guo Cai, Juan Zheng, Lu-Yu Chang
  • Publication number: 20240178320
    Abstract: A semiconductor transistor includes a semiconductor substrate with an original surface, an active region, a shallow trench isolation region, a shallow trench isolation region, a first conductive region and a second conductive region located within the active region, and a spacer. The active region is formed based on the semiconductor substrate and the active region has a fin structure. The shallow trench isolation region surrounds the active region and a gate structure of the semiconductor transistor crosses over the fin structure. The spacer contacts to a sidewall of the gate structure and on the fin structure. A width of the fin structure under the spacer is wider than that of the fin structure under the gate structure, the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure includes a rounded corner under the spacer.
    Type: Application
    Filed: November 23, 2023
    Publication date: May 30, 2024
    Applicant: Invention And Collaboration Laboratory Pte., Ltd.
    Inventor: Chao-Chun Lu
  • Publication number: 20240175162
    Abstract: Provided is a roughened copper foil capable of achieving both excellent transmission characteristics and suppression of powdering. This roughened copper foil includes a roughened surface on at least one side. The roughened surface has a roughness slope tan ? of 0.58 or less as calculated based on a mean height Rc (?m) and a mean width RSm (?m) of profile elements by formula Rc/(0.5×RSm), and a sharpness index Rc×Sku of 2.35 or less that is a product of the mean height Rc (?m) and a kurtosis Sku. Rc and RSm are values measured in accordance with JIS B0601-2013 under a condition of not performing a cutoff by a cutoff value ?s and a cutoff value ?c, and Sku is a value measured in accordance with ISO 25178 under a condition of not performing a cutoff using an S filter and an L filter.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 30, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Ayumu TATEOKA, Tsubasa KATO, Shota KAWAGUCHI, Po Chun YANG
  • Publication number: 20240178328
    Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.
    Type: Application
    Filed: May 1, 2023
    Publication date: May 30, 2024
    Inventors: Cheng-Hsien Wu, Chien-Lin Tseng, Sheng Yu Lin, Ting-Chang Chang, Yung-Fang Tan, Yu-Fa Tu, Wei-Chun Hung
  • Publication number: 20240178128
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.
    Type: Application
    Filed: January 22, 2023
    Publication date: May 30, 2024
    Inventors: Hong-Chih CHEN, Chun-Sheng LIANG, Yu-San CHIEN, Wei-Chih KAO
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240177995
    Abstract: A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Chun-Ming Lung, ChunYao Wang
  • Publication number: 20240176353
    Abstract: The present invention provides a method of alerting to stationary objects for vehicle. When a vehicle moves at a first speed, an optical scanning device, an infrared image extraction device, and an image extraction device extract a first optical scanning image, a first infrared image, and a first ambient image of the ambiance on one side of the vehicle. According to the fusion algorithm and the optical flow method, the first obstacle information of the first obstacle in the first image will be given. According to the location information of the first obstacle, the vehicle computer judges and generates an alert message when the relative distance is smaller than a distance threshold value and the obstacle volume is greater than a volume threshold value.
    Type: Application
    Filed: July 6, 2023
    Publication date: May 30, 2024
    Inventors: TSUNG-HAN LEE, JINN-FENG JIANG, SHIH-CHUN HSU, TSU-KUN CHANG, CHENG-TAI LEI, HUNG-YUAN WEI
  • Publication number: 20240178748
    Abstract: A power apparatus includes a substrate, a first power circuit, and a second power circuit. The substrate includes a first metallization region, a second metallization region, and a third metallization region which are separated from each other. The first power circuit is electrically connected to the first metallization region and the third metallization region, and is arranged across the second metallization region and fails to be in contact with the second metallization region. The second power circuit is electrically connected to the second metallization region and the third metallization region, and fails to be in contact with the first metallization region.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 30, 2024
    Inventors: Jason HUANG, Liang-Yo CHEN, Pi-Sheng HSU, Chun-Ming WEI
  • Publication number: 20240179829
    Abstract: A circuit board structure includes a build-up structure, a graphene layer disposed on the build-up structure, and at least one conductive pillar disposed on the graphene layer, the graphene layer includes an oxidized area not covered by the at least one conductive pillar and a non-oxidized area covered by the at least one conductive pillar, and the at least one conductive pillar is electrically connected to the build-up structure via the non-oxidized area.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 30, 2024
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventor: Chun Hung KUO
  • Publication number: 20240178177
    Abstract: A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 30, 2024
    Inventors: Ting-Yu Yeh, Chun-Hua Chang, Fong-Yuan Chang, Jyh Chwen Frank Lee
  • Publication number: 20240178215
    Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC China Company Limited
    Inventors: Xin-Yong WANG, Li-Chun TIEN, Chih-Liang CHEN
  • Publication number: 20240178548
    Abstract: An electronic device includes a housing, a circuit board, a first electronic component, a first conductive plate, and a first antenna. The housing includes a support member and a side frame surrounding a periphery of the support member. The support member includes a first conductive area. The circuit board is disposed on a surface of the support member and includes a feeding point on a surface of the circuit board. The first electronic component is disposed on the surface of the support member. The first conductive plate is disposed on a surface of the first electronic component. The first conductive area is disposed between the first electronic component and the side frame. The first antenna includes a first radiator, a first feeding part, and a first signal terminal. At least a portion of the first electronic component is disposed between the first conductive area and the circuit board.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 30, 2024
    Inventors: Wangik SON, Jungsik PARK, Incheol BAEK, Sunghyup LEE, Dongwoo SEO, Youngsoo CHUN, Byengsang JUNG
  • Publication number: 20240178961
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a first wireless device. The first wireless device receives, from a base station, a configuration of first reference signals on a first time-frequency resource. The first wireless device measures the first reference signals received from the base station to obtain first measurements for a direct path between the base station and the first wireless device. The first wireless device obtains second measurements for an indirect path between the base station and the first wireless device via a second wireless device. The first wireless device selects a communication path from the direct path and the indirect path based at least in part on the first measurements and the second measurements.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 30, 2024
    Inventors: Lung-Sheng Tsai, Chun-Hao Fang, Wei-Kai Chang, Chia-Hao Yu, Pei-Kai Liao
  • Publication number: 20240177790
    Abstract: A testing method includes the following steps of: accessing a memory chip to put the memory chip into a write leveling mode; inputting a strobe signal into the memory chip under the write leveling mode; adjusting signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip under the write leveling mode; generating a data signal according to the strobe signal under the write leveling mode; and determining types of the memory chip according to the data signal under the write leveling mode.
    Type: Application
    Filed: November 24, 2022
    Publication date: May 30, 2024
    Inventor: Wei-Chun CHEN
  • Publication number: 20240179192
    Abstract: A first device includes one or more processors configured to determine, based on one or more wireless signals, a candidate device list identifying one or more devices that are within a communication range of one or more sensing devices. The one or more processors are further configured to, based on a determination to initiate a shared media session with a second device of the candidate device list, receive a media stream including particular media content from a remote media service while the particular media content is being sent from the remote media service to the second device. The one or more processors are further configured to, based on the determination to initiate the shared media session, cause the particular media content to be output, based on synchronization information, contemporaneous with output of the particular media content at the second device.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 30, 2024
    Inventors: Andrew John LAISTER, John TURNER, Miran CHUN, Xiaoxin ZHANG
  • Publication number: 20240178052
    Abstract: A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Wang-Chun HUANG, Yu-Xuan HUANG, Hou-Yu CHEN, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240178937
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a transmitter. The transmitter receives a plurality of input bits. The transmitter encodes the plurality of input bits using a Trellis code to generate a plurality of output symbols. The Trellis code is configured to confine amplitude fluctuations between consecutive output symbols. The transmitter pulse shapes the output symbols in a frequency domain. The transmitter maps the pulse shaped symbols onto a plurality of subcarriers. The transmitter generates a time domain waveform based on the mapped symbols. The transmitter transmits the time domain waveform.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 30, 2024
    Inventor: Chun-Hsuan Kuo