Patents by Inventor Chun On To

Chun On To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dummy insertion for improving throughput of electron beam lithography
    Patent number: 11526081
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Semiconductor device and method for fabricating the same
    Patent number: 11527448
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Trench gate MOSFET and method of manufacturing the same
    Patent number: 11527643
    Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: December 13, 2022
    Assignee: uPI Semiconductor Corp.
    Inventors: Nobuyuki Shirai, Chun-Hsu Chang, Ming-Hung Chou
  • Semiconductor device and method for fabricating the same
    Patent number: 11527710
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pei-Jou Lee, Kun-Chen Ho, Hsuan-Hsu Chen, Chun-Lung Chen
  • Electrical connector having an insulative body with partition walls of different extent and with side walls provided with first through fourth installation grooves
    Patent number: 11527844
    Abstract: An electrical connector includes an insulating body, a first terminal group having a signal terminal pair and a ground terminal arranged on one side of the signal terminal pair, each signal terminal having a tail portion, a contact portion, and a body portion, the body portion having a covering portion and a free portion exposed to air, wherein there is a first center distance between the contact portions of the signal terminal pair, there is a second center distance between the free portions, and there is a third center distance between the covering parts, and a second terminal group forming a first mating port with the first terminal group, wherein the second center distance is smaller than the first center distance, and the third center distance is greater than the second center distance.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: December 13, 2022
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Chih-Ping Chung, Kuei-Chung Tsai, Chun-Hsiung Hsu
  • Driving circuit and electronic device for driving light emitting unit
    Patent number: 11527196
    Abstract: A driving circuit for driving a light emitting unit is provided. The driving circuit includes a driving transistor, a switch transistor, an emitting transistor, a first capacitor and a first compensation transistor. The switch transistor is coupled to the driving transistor. The emitting transistor is coupled between the light emitting unit and the driving transistor. The first capacitor is coupled to the driving transistor. The first compensation transistor is coupled to the first capacitor. A first end of the first compensation transistor and a first end of the emitting transistor receive same signal.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: December 13, 2022
    Assignee: Innolux Corporation
    Inventors: Ming Chun Tseng, Kung-Chen Kuo, Lien-Hsiang Chen, Chi Lun Kao
  • Circuits, equalizers and related methods
    Patent number: 11528003
    Abstract: A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Shu-Chun Yang
  • High temperature resistant wire and detector using the same
    Patent number: 11527336
    Abstract: A high temperature resistant wire is provided. The high temperature resistant wire comprises a carbon nanotube wire and a boron nitride layer coated on a surface of the carbon nanotube wire. The boron nitride layer is coaxially arranged with the carbon nanotube wire. A working temperature of the high temperature resistant wire in the air ranges from 0K to 1600K. A working temperature of the high temperature resistant wire in vacuum ranges from 0K to 2500K. A detector using the high temperature resistant wire is also provided.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: December 13, 2022
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Xin-He Yang, Peng Liu, Shi-Wei Lv, Duan-Liang Zhou, Chun-Hai Zhang, Feng Gao, Jian-Dong Gao, Kai-Li Jiang, Shou-Shan Fan
  • Conductive external connector structure and method of forming
    Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Method of checking normal power input and load of programmable AC power distributor at power-on state by light signal
    Patent number: 11526202
    Abstract: In a method of checking normal input power and load of a programmable AC power distributor in its power-on state, indicator lights are installed in an output ON button and an output OFF button. During power ON, a master switch is switched to an ON position to detect the input power and obtain a detection result through a change of the indicator light in the output OFF button, and then the output ON button is pressed to check the power-on state of the load and obtain a detection result by outputting the change of the indicator light of the button. Therefore, users can instantly know whether the input power and load are in a normal state during the operation of turning on the power distributor, and this method makes the operation of the power distributor safer and more convenient, and ensures a high quality of power supply.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: December 13, 2022
    Assignee: CHYNG HONG ELECTRIC CO., LTD.
    Inventor: Mu-Chun Lin
  • Dual-memory driving of an electronic display
    Patent number: 11527209
    Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 13, 2022
    Assignee: Apple Inc.
    Inventors: Bilin Wang, Tien-Chien Kuo, Kanghoon Jeon, Chun-Yao Huang
  • CARBON FIBER AND METHOD OF FORMING THE SAME
    Publication number: 20220389624
    Abstract: Carbon fiber and method of forming the same are provided. The method modifies proportion of a finishing oil to control a relation between a surface tension and a particle size of the finishing oil, and thus penetration of the finishing oil into an interior of the carbon fiber is avoided. Therefore, the carbon fiber can have both low oil residues and a high strength.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 8, 2022
    Inventors: Kun-Yeh TSAI, Chia-Chi HUNG, Wen-Ju CHOU, Ching-Wen CHEN, Chia-Chun HSIEH, Shi-Jie LIN, Long-Tyan HWANG
  • SEMICONDUCTOR FABRICATION APPARATUS
    Publication number: 20220392782
    Abstract: An apparatus for fabricating a semiconductor device has a housing defining a buffer chamber, a plurality of reactor ports formed in the housing for establishing interfaces with a plurality of process chambers that are to receive a wafer during a fabrication process to fabricate the semiconductor device, a wafer positioning robot positioned within the buffer chamber to transport the wafer between the plurality of process chambers through the plurality of reactor ports, a purge port formed in the housing for introducing a purge gas into the buffer chamber, a pump port formed in the housing for exhausting a portion of the purge gas from the buffer chamber, and a first flow enhancer that directs the purge gas flowing in an axial direction along a longitudinal axis of the purge port into the buffer chamber in a plurality of radial directions relative to the longitudinal axis.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 8, 2022
    Inventors: Chih-Tsung LEE, Sheng-chun Yang, Yun-Tzu Chiu, Chao-Hung Wan, Yi-Ming Lin, Chyi-Tsong Ni
  • SUPPORTER
    Publication number: 20220393713
    Abstract: A supporter is provided. The supporter includes a base, a holder, a positioning member, a connecting rod assembly, and a power assembly. The holder is connected to the base and has a through-hole. The positioning member is disposed in the through-hole of the holder. The connecting rod assembly is disposed on the holder and connected to the positioning member. The power assembly is movably disposed on the holder via the connecting rod assembly. Accordingly, the power assembly is movable in response to the position of the electronic device, which achieves good recharge efficiency whether the electronic device is arranged upright or horizontally.
    Type: Application
    Filed: August 10, 2021
    Publication date: December 8, 2022
    Inventors: Chun-Chien CHEN, Chen Yi LIANG, Tzu-Ying CHEN
  • ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20220392905
    Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 8, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang, Chang-Chien Wong, Te-Wei Yeh, Sheng-Yuan Hsueh
  • METHOD AND COMPOSITION FOR REGULATING PLANT ARCHITECTURE
    Publication number: 20220386546
    Abstract: A method for regulating plant architecture includes applying a composition containing ?-Aminobutyric acid (GABA), glutamic acid and choline chloride to a plant. The composition for regulating plant architecture is also provided.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 8, 2022
    Inventors: Yu-Lun Liu, Cho-Chun Huang, Gui-Jun Li, Kai Xia
  • Display
    Patent number: D972559
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: December 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Suet Chan Law, Chun Long Goh
  • Protective information handling system case
    Patent number: D972572
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: December 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Peter Clark, Richard W. Guzman, Sean P. O'Donnell, Georg Todtenbier, Oscar Coutinho, Yung-Chun Chen, Ming-Chiao Lee
  • Peripheral camera
    Patent number: D972616
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: December 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Celia Law, Chun Long Goh, Hang Du, Wai Mun Lee
  • Masks formed based on integrated circuit layout design having cell that includes extended active region
    Patent number: RE49331
    Abstract: A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung Lu, Li-Chun Tien, Hui-Zhong Zhuang, Chang-Yu Wu