Patents by Inventor Chun-Pei Wu
Chun-Pei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220406819Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.Type: ApplicationFiled: June 21, 2021Publication date: December 22, 2022Inventors: YUNG-CHIH TSAI, CHIH-PING CHAO, CHUN-HUNG CHEN, SHAOQIANG ZHANG, KUAN-LIANG LIU, CHUN-PEI WU, ALEXANDER KALNITSKY
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Patent number: 11088136Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.Type: GrantFiled: February 25, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10991688Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.Type: GrantFiled: November 26, 2018Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20200194430Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10622351Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20190109132Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20190096881Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 10157916Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: GrantFiled: April 10, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Publication number: 20180294261Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.Type: ApplicationFiled: April 10, 2017Publication date: October 11, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
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Patent number: 8927370Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.Type: GrantFiled: July 24, 2006Date of Patent: January 6, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Chun-Pei Wu
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Patent number: 8300462Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.Type: GrantFiled: February 6, 2012Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
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Publication number: 20120134209Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
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Patent number: 8183106Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.Type: GrantFiled: July 26, 2006Date of Patent: May 22, 2012Assignee: Macronix International Co., Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Meng Hsuan Weng, Tzung Ting Han, Ming Shang Chen, Chun Pei Wu
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Patent number: 8129242Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.Type: GrantFiled: May 12, 2006Date of Patent: March 6, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Tian-Shuan Luo, Chun-Pei Wu
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Patent number: 8120956Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.Type: GrantFiled: February 19, 2010Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
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Patent number: 8017480Abstract: A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.Type: GrantFiled: June 13, 2006Date of Patent: September 13, 2011Assignee: Macronix International Co., Ltd.Inventors: Chen-Chin Liu, Chun-Pei Wu, Ta-Kang Chu, Yao-Fu Chan
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Patent number: 7910453Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.Type: GrantFiled: July 14, 2008Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeff J. Xu, Chia-Ta Hsieh, Chun-Pei Wu, Chun-Hung Lee
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Publication number: 20100290284Abstract: An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.Type: ApplicationFiled: February 19, 2010Publication date: November 18, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Pei Wu, Chia-Ta Shieh, Chih-Wei Hung, Mars Chen
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Publication number: 20100006974Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeff J. Xu, Chia-Ta Hsieh, Chun-Pei Wu, Chun-Hung Lee
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Patent number: D1024932Type: GrantFiled: March 10, 2022Date of Patent: April 30, 2024Assignee: WALSIN LIHWA CORPORATIONInventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin